ESS Sabre Reference DAC (8-channel)

[Coris]

BTW, the ESS9018 is not an microprocessor which need more current/power, get hot, or is been stressed when one overclocked it... Is necessary to precise here that this chip is an digital to analogue converter? Only an very sophisticated one. The microprocessor in it is not affected by the (f. ex.) 25% overclocking... but the sound out of it, it is... in a better way.
In my experiments I have used even 150Mhz to clock this chip, and nothing exploded... Only the sound out of it it were not usable.

[KlipschKid]

Originally Posted by farhun

I've already purchased one along with a fast USB to I2S board for this DAC from the same vendor, and received both of them today.

DAC board looks neat! The hybrid components are fairly apart from each other, I don't see a big challenge in putting them on, even few mandatory SMD parts. There are few ambiguous spots that I couldn't figure totally yet, though! Few components need to be identifed or clarified, but I think they don't pose a problem either.

I believe this board have already attracted some DIYer's attention, there will be more to respond here soon!

In any case I'm not very experienced with DAC boards, and have limited experince with SMD stuff,but I think it would be much appreciated if someone who is more apt and experienced can share the experience with this board.

How's the build going ? Is it working yet ? How about the BOM - any problem getting parts etc ?

Qusp/Coris - the other thing worth mentioning is that it is US$7 compared to the US$30 for a Crystek. I'll get one of the Ebay boards and try both a Crystek 22.5792MHz and the Epson Saw 125Mhz, and a Euroquartz XO91 50Mhz.

[Bunpei]

Originally Posted by ghmfranken

I am observing values of 8 and 9 on register 27 (ES9018 Status (Read-only)) on my EV board. In the Help of the Sabre GUI I can only find that values 0-3 are described and 4-7 are reserved. Where can I find more detailed information on the meaning of the ES9018 registers and register 27 in particular?

"glt" is unlikely to answer your question. (I would thought he was the best person.)

I'm afraid you have the read-out decimal values confused with bit-position definitions.

If the observed values 8 and 9 are in a decimal expression, bit patterns in binary expression are;
decimal 8: binary 0001000
decimal 9: binary 0001001

On the other hand, the datasheet of ES9018 shows;
[7:4] RESERVED
[3] dsd_pcm
[2] spdif_valid
[1] spdif_en
[0] lock

The numbers used above define not decimal values but positions of the flag bits.
Therefore, the decimal value 8 and 9 mean,
[DSD mode] & [unlock] and [DSD mode] & [lock],
respectively.

Or are you asking undocumented meaning of the RESERVED bits?

[Bunpei]

Originally Posted by qusp

because i'm running synchronous clocking with dual lower jitter clocks already (45.1584/49.152MHz, shortly doubling that 90.3168/98.304 with even lower jitter NDK parts), ...

Have you observed a significant difference between 40s MHz clocks and 90s MHz
clocks?

[qusp]

Originally Posted by Coris

BTW, the ESS9018 is not an microprocessor which need more current/power, get hot, or is been stressed when one overclocked it... Is necessary to precise here that this chip is an digital to analogue converter? Only an very sophisticated one. The microprocessor in it is not affected by the (f. ex.) 25% overclocking... but the sound out of it, it is... in a better way.
In my experiments I have used even 150Mhz to clock this chip, and nothing exploded... Only the sound out of it it were not usable.

right, so we have established that you dont know how the dac works, nor have you at any time checked what the power consumption is, or how your mods effect it.

its also pretty logical that running higher speed uses more power. the ESS actually DOES contain a microprocessor.

how do you explain a device that switches with relation to each clock cycle and uses energy doing so, not using more energy if it has to switch more often? perhaps ESS have discovered perpetual motion?

I did not expect to have to explain such basic science to you....

ahh I see your testing methods extend to whether or not the dac chip explodes, or stops working correctly and you deemed it OK to simply run it at as high a speed as you can while it still outputs sound?

mad science...

Bunpei, I havent got the double speed clocks yet, Acko needs to do more work integrating it with fifo. i'm talking about the Turboclock with NDK

[qusp]

Originally Posted by KlipschKid

How's the build going ? Is it working yet ? How about the BOM - any problem getting parts etc ?

Qusp/Coris - the other thing worth mentioning is that it is US$7 compared to the US$30 for a Crystek. I'll get one of the Ebay boards and try both a Crystek 22.5792MHz and the Epson Saw 125Mhz, and a Euroquartz XO91 50Mhz.

$7 is still a waste of money (and hobby time, which matters more to me) if it provides no benefit. I recommend getting the Crystek in the 45.1584MHz even if you are only running 44.1

[Bunpei]

Originally Posted by Bunpei

I have thought why the method[synchronous master clocking] is better than an asynchronous master clocking for a long time. I'd like to explain my considerations on a series of posts and to request your frank comments.

I think I got no negative comments on this topic.
RayCTech and qusp told us about their trials on synchronous master clocking and, at least, they did not show their negative opinions on the method.

My basic message is;
"ES9018 architecture has no mean to generate any shorter timing than one tick of master clock, for example 10ns for 100MHz MCLK. An asynchronous master clocking method brings the maximum 10ns quantum error along a time axis. On the other hand, a synchronous clocking can make the error to zero in theory."

If you think the message is incorrect, please post your idea with any certain supporting facts.

[Bunpei]

Originally Posted by Bunpei

decimal 8: binary 0001000
decimal 9: binary 0001001

I'm very sorry! I made a terrible mistake in the previous post.

<Correct>
decimal 8: binary 00001000
decimal 9: binary 00001001

Left-hand side is the Most Significant Bit(MSB), bit position 7 and right-hand side is the Least Significant Bit(LSB), bit position 0.

[Bunpei]

Originally Posted by qusp

Bunpei, I havent got the double speed clocks yet, Acko needs to do more work integrating it with fifo. i'm talking about the Turboclock with NDK

Thank you very much for your explanation.

[qusp]

synchronous mode is different, I think better yes, definitely not worse. I thought I had already commented on this earlier in the thread; though at that time I had a worrying glitch associated with sync mode that I had never had with Async. I have not had this since changing to the 45.xx/49.xx clocks. its hard to describe the difference, a definite bonus is there is much less warm up time on the DAC and the dropouts are zero. imaging seems to be more solid and high frequency retains detail, but never hyped. sorry i'm not very good at the flowery audiophile prose.

no worries Bunpei, i'll update when I receive the AK701, i'm looking forward to it.

Obviously I simplified the 25% faster clock = 25% more power consumption, its not so exact, but along those lines on many of the pins, not all though. the pad ring and logic supplies more than others. I havent done any further measurements, but 100MHz async clock uses more power than 80MHz did. depending on the power supplies it may not stress them, but with some of the flea type voltage reference + opamp followers, the opamps dont have large current capacity/overhead.

it does stress the dac more though, usually warnings for max operating conditions have some basis.... it seems to have been confirmed by not working at 150. i'm not a Dac whisperer though, I need to make measurements of such things, I cannot tell the exact extent and health of the dac by listening to it or touching it.