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Old 17th June 2012, 02:36 AM   #1941
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Quote:
Originally Posted by gentlevoice View Post
Hi - just briefly bumping the thread with a question:

Any of you have datasheets (detailed one) for the ESS9012/9018 and ESS9102 ADC? I'd appreciate seeing the datasheet if possible ...

Best regards,

Jesper
Just request one from ESS. You need to sign a non-disclosure agreement, but it's still pretty easy.
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Old 18th June 2012, 07:39 AM   #1942
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Thanks Brian,

I'll do that.

Best regards,

Jesper
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Old 20th June 2012, 04:40 PM   #1943
Coris is offline Coris  Norway
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Quote:
Originally Posted by gentlevoice View Post
Hi - just briefly bumping the thread with a question:

Any of you have datasheets (detailed one) for the ESS9012/9018 and ESS9102 ADC? I'd appreciate seeing the datasheet if possible ...

Best regards,

Jesper
Hi
Just write to this address: bryans@shawelectronics.com
You do not need to sign any non-disclosure agreement. The ESS has cancelled the confidentially status on this document from a years ago or so...
I personally experienced no answer ever from ESS at my inquiry on this subject..

Last edited by Coris; 20th June 2012 at 04:43 PM.
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Old 20th June 2012, 06:53 PM   #1944
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Hi Coris,

Thanks for the link - I wrote ESS some days ago and I'll just give them a few days more to reply - otherwise I'll write to the link you gave me.

Thanks again!

Jesper
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Old 8th August 2012, 08:30 PM   #1945
Coris is offline Coris  Norway
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Quote:
Originally Posted by gentlevoice View Post
Hi Coris,

Thanks for the link - I wrote ESS some days ago and I'll just give them a few days more to reply - otherwise I'll write to the link you gave me.

Thanks again!

Jesper
Just curious if you`ve got an answer from ESS...?
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Old 11th August 2012, 04:32 PM   #1946
Bunpei is offline Bunpei  Japan
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Default DSD playing mechanism in Sabre32 architecture

I like the sound characteristic of DSD256 the best among input signal formats compatible to Sabre32.
In the case of TI PCM/DSD179x DAC chips of "Advanced Segments" architecture, they say "only an analog FIR is applied to DSD input signals."

On the other hand, how is a raw DSD input proceesed in our Sabre32 DAC chip?
Has anyone read or heard technical details of DSD signal processing in the chip?

My guess is;
As Sabre32 has 6 bit multilevel DA conversion units for Delta-Sigma modulation, a raw DSD 1 bit Delta-Sigma modulated signal might be decimated to 6 bit Delta-Sigma modulated signal through a FIR stage internally.
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Old 20th November 2012, 02:49 PM   #1947
Bunpei is offline Bunpei  Japan
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Default DSD512 Play with a synchronous master clocking

These days, I have been trying a play of DSD512 sources on ES9018 (TPA Buffalo II) with a synchronous master clocking of 90.3168/98.304MHz. However, the playing is very unstable and suffering a burst of DSD specific noises.
Does anyone establish a stable play of DSD512 with a 90MHz synchronous master clocking?
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Old 11th December 2012, 08:21 AM   #1948
roender is offline roender  Romania
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Quote:
Originally Posted by wktk_smile View Post
In the Sabre dac app note, ESS recommends inverted MCLK when that's synchronous, although they only says
"The inverted MCLK ensures that the Sabre noise as low as possible." and there's no further explanations.

Anyone tried these?

As far as I tried myself, (I stolen MCLK from transport via LVDS and made inverted at the LVDS receiver input.)
I felt it's slightly better in SQ, but I can't say surely it's better because I haven't done strict A/B comparison yet.

Besides, I have no skill and equipments to measure noise performance correctly.

I 'm just curious what other people found or felt in synchronous + inverted MCLK.
Shall I presume that inverted I2S signals would have the same efect as inverted MCLK?
I intend to design a dual clock board based on CCHD975 oscilators (45.1584 MHz and 49.152 MHz) and feed the BIII directly from them and SDtrans after an D flip-folp configurated as divider by 2. SDtrans will command which clock is required to run based on the played file sample rate.
It will be very easy to take the clock for SDtrans from inverted Q or non inverted Q therefore all the i2S signals will be inverted or non inverted in rapport with DAC's MCLK
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Old 11th December 2012, 12:31 PM   #1949
rolls is offline rolls  Switzerland
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Quote:
Originally Posted by roender View Post
Shall I presume that inverted I2S signals would have the same efect as inverted MCLK?
I intend to design a dual clock board based on CCHD975 oscilators (45.1584 MHz and 49.152 MHz) and feed the BIII directly from them and SDtrans after an D flip-folp configurated as divider by 2.
Oscillator belongs to the dac, as near as possible. Better to slave the transport. I am looking for a way to slave my transport as well:
I use a lampizator modyfied Denon. it has several clocks, generated by a 27Mhz Quartz and a PLL chip. So I am in need of a 108Mhz Oscillator, which I have not seen yet.
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Old 11th December 2012, 12:38 PM   #1950
roender is offline roender  Romania
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Quote:
Originally Posted by rolls View Post
Oscillator belongs to the dac, as near as possible. Better to slave the transport. I am looking for a way to slave my transport as well:
I use a lampizator modyfied Denon. it has several clocks, generated by a 27Mhz Quartz and a PLL chip. So I am in need of a 108Mhz Oscillator, which I have not seen yet.
Did I said something else? The dual oscillator board will be integrated with the DAC, very close to Sabre chip, and MCLK frequency will be commanded by the transport, SDtrans in my case, therefore the BIII DAC will be in sync mode.
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