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Old 30th January 2011, 02:34 AM   #1781
AR2 is offline AR2  United States
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Quote:
Originally Posted by Bunpei View Post
A Japanese technology oriented vendor, Fidelix, provides a board level component.
http://www.fidelix.jp/img/I2S-HDMI.gif
http://www.fidelix.jp/img/I2S-HDMI%20PCB.jpg


The receiver module incorporates an isolator device and its power can be supplied from a transmitter side.

Its price is 15,000 JPY. Their contact address is info@fidelix.jp
Thank you, greatly appreciated. This seems like a great product, but man the price is steep - $ 182!
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Old 30th January 2011, 03:24 AM   #1782
Bunpei is offline Bunpei  Japan
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Originally Posted by AR2 View Post
but man the price is steep - $ 182!
You can make it yourself based on the schematic. However, soldering around HDMI connector seems very difficult.
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Old 30th January 2011, 04:03 AM   #1783
AR2 is offline AR2  United States
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Originally Posted by Bunpei View Post
You can make it yourself based on the schematic. However, soldering around HDMI connector seems very difficult.
Yes, you are correct. I am not worried about soldering, did a lots of SMD work, but it is board that is my problem. I never did PCB on my own and without that is difficult.
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Old 1st February 2011, 09:48 PM   #1784
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Question for you engineers: I'm lifting I2S from single circuit board vias and supplying multiple DAC chips. Signal clocks, for example, go from 1 source to 5 different destination chips. It does work to daisy-chain these inputs from one board to the next. Still, is it preferable for each input to originate as close to the source as possible? TIA!

Frank
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Old 1st February 2011, 10:28 PM   #1785
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Homeruns would be preferable. you actually might want to buffer the signals, since you are paralleling so many sinks.
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Old 1st February 2011, 10:48 PM   #1786
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Thanks Brian! I'll start with short home runs and troubleshoot as necessary after all the I/O is restored... Chassis work seems so mundane after the test-bench setups have been playing beautifully!
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Old 2nd February 2011, 12:41 AM   #1787
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Originally Posted by BrianDonegan View Post
Homeruns would be preferable. you actually might want to buffer the signals, since you are paralleling so many sinks.
I would think that buffering would be advisable and necessary but I do not know what is used for buffering of I2S. Could you please elaborate little bit more in detail what is used for this purpose. I know how to do it for S/PDIF but I do not think that same way could be done for I2S.
Thank you.
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Old 2nd February 2011, 01:31 AM   #1788
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Originally Posted by francolargo View Post
Thanks Brian! ... and troubleshoot as necessary after all the I/O is restored...
...looked into this a little more. In my case, I see that the source is a Xilinx XC9500 series CPLD. The data sheet is not helpful in forecasting specific drive limitations except to say that pulses should be limited to 200mA and the overall junction temps should be 70C or less even though it is tolerant much hotter. So when I power back up I'll monitor that chip and make sure it is not running hot. I could give it a heatsink! Also, there are two onboard DACs that I could deactivate. I'm taking considerable care to keep all the I2S lines a minimum length, so my fingers are crossed that a buffer won't be necessary because I don't know where I'd put it.
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Old 2nd February 2011, 05:54 AM   #1789
Zoran is offline Zoran  Serbia
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Hi,
I have one Q
(Maybe Brian is most qualified person to answer...)
I have Sabre dac playing (very good)
in factory settings 80MHz MCL, 24bit, i2S, Ioutput, 50KHz/fast roll-off, jitter reduction
and L/R 4 X DAC ballanced out.
.
My Q is can I set the PIC to SET all DAC units inside to single ended Iout
to one channel?
I want use single chip per channel and I do not need ballanced outs...
?
Thanks
And thankk You Brian for the great great DAC chip
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Old 2nd February 2011, 06:00 AM   #1790
Zoran is offline Zoran  Serbia
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And just one q more lplease
:
can I employ 90.3168 MHz master clock with Sabre dac?
( 90.3168 MHz = 4 x 22.5794 MHz = 4 x 512 x 44.1 KHz )
thanks
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