Re: Digital Filter
What type of input did you have in mind. Simply a superfast "I2S" port that skips the data over the FIR? If this is what peple want, it will be easy to add in a future rev.
For the current chip, you could run the I2S data in at up to 351.5625kHz (thats 22.5MHz on the Data_Clk) and it should be fine. In that case you will want to have an 80MHz XI clock speed or so (just needs to be greater than 192*FS, so 67.5MHz, but adding a bit more speed helps the jitter blocker when LOTS of jitter is present)
Then is you dont like the Sharp OSF filter, you can choose the slow rolloff, this is actually a SINC responce filter that has been set such that the -3dB point is exactly 20k/44.1k or 0.4535FS. So if you run the data in at 151kHz and use the sloww rolloff filter, you will get a non-rippling filter with a -3dB point at 159kHz. IF this can work for you, then its already to go.
Thanks
Dustin
FuriousD said:
What type of input did you have in mind. Simply a superfast "I2S" port that skips the data over the FIR? If this is what peple want, it will be easy to add in a future rev.
For the current chip, you could run the I2S data in at up to 351.5625kHz (thats 22.5MHz on the Data_Clk) and it should be fine. In that case you will want to have an 80MHz XI clock speed or so (just needs to be greater than 192*FS, so 67.5MHz, but adding a bit more speed helps the jitter blocker when LOTS of jitter is present)
Then is you dont like the Sharp OSF filter, you can choose the slow rolloff, this is actually a SINC responce filter that has been set such that the -3dB point is exactly 20k/44.1k or 0.4535FS. So if you run the data in at 151kHz and use the sloww rolloff filter, you will get a non-rippling filter with a -3dB point at 159kHz. IF this can work for you, then its already to go.
Thanks
Dustin
I2S Data width
Hi Dustin,
Am I correct in assuming that the 352kHz I2S input has data width of 24Bits? In which case i have to restrict my filtering to a 24-Bit data width which is not good. The advantage of the Texas part is that when you bypass the filter you have access to a 32-bit data width (Admittedly only at 192kHz but I can live with that).
I have a good idea what you have done after this, but the filter is the key to going from good sound to great sound. When I designed the concept of the Chord DAC64 filter it took a fairly unremarkable D2A concept and made it sound excellent.
I would love to be able to take an improved variant of that concept and couple it with the excellent performance of your modulator and DAC, but 24-bits is just not going to cut it.
If your filter has several stages, can we break in further down the line? at a wider bit width or faster rate?
Is there a work around on this? and if so what sort of time frame would this based upon.
Hi Dustin,
Am I correct in assuming that the 352kHz I2S input has data width of 24Bits? In which case i have to restrict my filtering to a 24-Bit data width which is not good. The advantage of the Texas part is that when you bypass the filter you have access to a 32-bit data width (Admittedly only at 192kHz but I can live with that).
I have a good idea what you have done after this, but the filter is the key to going from good sound to great sound. When I designed the concept of the Chord DAC64 filter it took a fairly unremarkable D2A concept and made it sound excellent.
I would love to be able to take an improved variant of that concept and couple it with the excellent performance of your modulator and DAC, but 24-bits is just not going to cut it.
If your filter has several stages, can we break in further down the line? at a wider bit width or faster rate?
Is there a work around on this? and if so what sort of time frame would this based upon.
The ESS DAC itself uses a user selectable bit width quantiser. Normally set around 6-Bits. This is the actual DAC resolution. So Delta Sigma modulation is being used to sacrifice out of band noise perfromance in favour of increasing in band SNR.
If you read the datasheet for the ESS part you will see that it has an internal data path of 48-Bits. You will note that the DAC64 has an internal data path of 64-Bits. There is a good reason for this.
Whilst 24-input bits gives a theoretical DNR of 144dB, if the data path has out of band components at -144dB prior to the actual DAC stage internally, then the massive out of band gain of the modulator will amplify these components up to a level that is very much significant.
24-Bit input data x 24 bit tap coefficients in the filter = 48-Bit result. To input that back into a 24-bit input, you would need to dither or just truncate it back down to 24-Bits and that is where the problems begin.
Re: Re: Re: I2S Data width
I started this thread. I believe the topic is specifically based around my initial question of how us DIYers get our hands on one or two chips in low volume, and if anybody had already used it and could give feedback on how it sounds given the impressive specs.
Those questions remains unanswered. It seems the chip is really still a prototype and is yet to undergo a few revisions. There has only been technical questions and answers about certain aspects of the chips design implementation and some interfacing options. They only come in handy if I can get hold of it to do something with it.
abzug said:
I started this thread. I believe the topic is specifically based around my initial question of how us DIYers get our hands on one or two chips in low volume, and if anybody had already used it and could give feedback on how it sounds given the impressive specs.Those questions remains unanswered. It seems the chip is really still a prototype and is yet to undergo a few revisions. There has only been technical questions and answers about certain aspects of the chips design implementation and some interfacing options. They only come in handy if I can get hold of it to do something with it.
Re: Re: Re: Re: I2S Data width
Isn't there chip aviable from Brian at Shaw? I talked to him myself and he said he has some for people.
InfiniteGain said:
Those questions remains unanswered. It seems the chip is really still a prototype and is yet to undergo a few revisions. There has only been technical questions and answers about certain aspects of the chips design implementation and some interfacing options. They only come in handy if I can get hold of it to do something with it.
Isn't there chip aviable from Brian at Shaw? I talked to him myself and he said he has some for people.
So who are you then? Clearly you know alot about Chord, but no quite enough. I admit that I don't know Mike Dixon (after my time), was he responsible for the SMPS that gave the first DAC64's >4nS of jitter? (See Sterephile for details) and yes I'm sure that Rob would love the world to believe that he was responsible for the filter design in the DAC64. He has made a good living out of Zetex off the back of that myth. Implementation and design are two very different things. I don't think that I can add anything more than that without being knuckle wrapped.
I still have the original Matlab files for the filter design, which when I left was a 2/8 channel surround sound processor implemented in FPGA based on 3x Spartan II's (Stop me when you recognise the sound of any of this). The 8 Channel version was simply a restricted version of the original 2-channel design which used the full resource of the 3x devices. Left Filter, Right Filter and DAC Modulator in the third.
The filter was what set the DAC alight and has one fundamental concept that differs from what Texas, AKM, Analog and from the datasheet shown what ESS do as well.
(Sorry I know that this is meant to be a glory be to ESS thread, but I am still interested in doing a super DAC as a project and would be happy to share designs, schematics & results with anyone who is interested. I fully agree that if you want to participate on this forum then you need to contribute not just use others to further your own designs.).
DAC's are all about 4 main areas. Clock, PSU, Modulator & Filter. It looks on paper like the Modulator section is about as good as it gets, the clock as suggested above can improve the demoboard sound, so that backs that one up. I will shortly be investing in some very low phase noise VCXO's if anyone is interested in group purchase then let me know.
That just leaves the PSU and the filter. The Clock and DAC PSU's are about as vital as they get, and I can get better CD sound from a crystal simple CS4390 that i've ever managed elsewhere simply by attending to the PSU on the clock and the DAC. The next step would be implement this onto something capable of much more.
By Dustin's flippant remark about discarding 8-bits clearly i've annoyed him by suggesting that design could be improved by the filter. I hope that he does include a filter bypass on future revisions as per the wolfson or the texas, as I would love to see how far CD performance can be taken with his excellent technology.
Hi FuriousD,
Its wan't intended to come across this way.
I agree with what your say about needing more then 24bits to drive into the modulator, this is exactly why I nuged it up to 28bits. I went as far as 36bits in prototypes, but then opted to drop to 28 since in my design that is where the digital noise floor dropped out of site. Future rev will have something like this.
That being said thre are still some filtering going on at the 28 bit level before the signal hits the noise shaper, or even the jitter blocker for that matter.
Thanks
Dustin