ESS Sabre Reference DAC (8-channel)

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Hi Bunpei

Sorry for not be so very accurate to answer to all your questions.

The reported issue it appear at a clock frequency of 120Mhz, and up. At 125Mhz this cracklings are very obvious, when the zero bits sequence is present. At higher frequency (133Mhz) these disturbances are over all the playback. At 150Mhz the chip does not convert anything.
At 108Mhz and 112Mhz the ES9018 work just fine, with improved sound quality (run it on both PCM and DSD). As I previously mentioned, I do not know the explanation of these improvements. The sampling frequency is the same, so I can not explain a quite obvious increase in fidelity at higher clock frequencies, than max. specified in datasheet. It may happen because some additional processes inside the chip are running at a higher speed... Well, this about such explanations it may be another story.

Thanks for your comments/answers at my questions in above post.
I may say that my "heavily modded" Oppo player is now an old modded device, which by the way, it works just exceptional. Well. some fine tunings, and some more professional made modules for the player are on the way, but mainly this job is done since quite a time.
Actually my previous questions was in connection with the newest Oppo product, HA-1, which start to be more and more heavily modded too...:D
The designers of this device did not use the Lock pin, and I was just wondering what informations it can come up from this output. After connecting a LED to it, I was surprised to see that no any information is out of it, as it stay always on. I was thinking that because I used from it 6mA on my LED, it was too much for that output, and I made it on forever...But your answers make sense, and I can also think that the designers used the safest setup for the chip, so that the customers may not have unlock problems..

What is quite interesting about my experiences with overclocking, is that the ES9018 in this HA-1 does not accept in the same way as the same chip in BD105 model, these higher clock frequencies.
While the DAC in BD105 it can run on 120-125Mhz clock without any problems. the same frequency used for HA-1 does not work well. As I remember, Joe Rasmunssen reported that he experienced problems when was running on the clocks frequencies which worked for me.
I just think it may be interesting to find out why such different behaviours. This is definitely not because the different chip batches or production issues. It may have something to do with the external hardware configurations around the chip, as with its implemented software/firmware. Now I can see myself that for these two Oppo devices I have worked on, the DAC chip behave quite different when about overclocking...

Keeping searching...
 
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Hi AAK

Well, the tests are mainly based on what I can hear. The differences are just obvious. But I do not know how to quantify or objectify these results. What to measure in all this, and how?

When about A/B testing, I think the best way to be tested so, is if somebody else will try himself similar configurations, and will write down his observations, conclusions, findings.
So far I can see, is only me who do these experiments, and claim on improvements... I just wonder why are so many sceptics in trying such, and why anybody else is not coming here saying: well, I tried it overclocking and I can not notice any improvements...
Even more, one do not have to try overclocking, but only using of an 50Mhz oscillator, and a 100Mhz one to clock an ES9018 chip it may be enough to notice the improvements in the outputted sound (at higher clock frequency). Nobody have experienced this?

Else, referring to my last posts here, about this always ON Lock on my device, I can say that after some more tests, using different sample rates and files, I could see this Lock signal in action. So, it works well, and normal at least...
 
Hi Coris,

To know for sure if the improvements are real a subjective A/B comparison test is really needed. I'd be surprised if there's a noticeable difference between 100, 108, and 112Mhz. Between 50Mhz and 100Mhz maybe so. If I ever get around to doing an A/B using different frequencies on my ES9018 DAC I'll let you know.

Best regards,

Al
 
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Experimenting with the DAC stage in Oppo new product, HA-1, I found out that the system (whole device) does not boot up if the clock signal is not present at the ES9018 clock pin. The DAC oscillator it feed exclusively the DAC chip clock pin, and the rest of the processor chips it have its own oscillator. This assertion I verified by lifting it up the chip clock pin, and connect directly to it the clock signal.
The question here (in connection with the ES9018 way to work) is how this chip it may give the message to the rest of the system, about its status (and especially if the clock is present at its pin).
I can not see a hardware possibility, as the chip do not have a such digital output.
It may be used the Lock pin as a status information, but this supposition it seems not to be true. The Lock signal it become high, quite late after the system got it up and is running.
My supposition is that the system get the information out of the ES9018 chip, by reading some of its registry bits, in boot up sequence.
Now my question is: it have ES9018 a such registry where the information about the chip status it can be outputted/read it?
I got through the datasheet of the chip, and I could`n see something in this respect.
I could also notice that if clock signal level become under a certain value, the Lock pin goes low, while the rest of the system does not seems to register a wrong status for the DAC chip...
Have someone some knowledge about?

And something else/more about the ES9018 functionality.
I could notice, comparing some other Oppo products, which include this DAC chip, that are differences in how the chip accept the clock signal levels on its clock input pin.
While the ES9018, configured in some player systems, it can accept a quite wide range of clock signals levels, and the clock input pin it can be easily adapted to trigger at a certain clock signal level, the same is not possible in this last headphone amplifier, this DAC is integrated to.
It looks to me that ES9018 it may have the possibility to be (software) configured about how the clock pin(s) should work. If this it may be true, then it may be something quite new, and unknown (for the most of this chip users, except some "chosen" ones...).


Some thought about?
 
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Bunpei, may I repeat the question posted a few lines above, and address it to you? Thanks.
What does pseudo- and true-differential output mean if applied to the Sabre? Hope you do know.
If to speak of traditional definition of these terms, the I/U converter scheme must be quite different for each.
 
the system (whole device) does not boot up if the clock signal is not present at the ES9018 clock pin.

My guess would be that :

- ES9018 probably needs a clock to reset itself properly. For example, since the filters are modifiable, they are probably copied from ROM to RAM at power-up, and copying memory needs an address counter, thus it needs a clock. Also the usual practice is to assert RESET until the clock is stable, otherwise when the clock comes up, it may have some cycles that are out of spec (ie, too short) and crash the logic.

- Also it is probable that ES9018 needs a clock for the I2C bus interface to work. If it does not reply to I2C commands, perhaps the main processor gets stuck waiting for ES9018.

It looks to me that ES9018 it may have the possibility to be (software) configured about how the clock pin(s) should work. If this it may be true, then it may be something quite new, and unknown (for the most of this chip users, except some "chosen" ones...).

The 9018 MCLK Input can be connected to a crystal (together with MCLK output) to make a crystal oscillator. Using a dedicated oscillator probably has much lower jitter though.

Clock input pins which accept the low levels from a crystal are usually able to accept almost anything provided it's not above the max ratings, for example the clock can be capacitive or transformer coupled, or even quite attenuated, without worrying too much about CMOS levels. However, noise (ie, jitter) will still be minimized if the clock has clean fast edges and proper level, so it isn't a reason to be sloppy.




Some thought about?[/QUOTE]
 
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Thanks for replay.

I think the most plausible it may be this I2C interface, which have to be up in a special way (maybe send it some "good" status) which the main processor look for at power on/boot up sequence. Without a clock this I2C it may be in a random state. Also without a clock the chip reset may not work at all. The reset may put some bits so to be interpreted by the processor/system. But a reset it can be also triggered by the power presence at the chip power rails... Well, we do not know exactly what kind of reset(s) work in this chip, and how it was designed to be...
However, it make sense your explanations...

When about clock signal levels, it may be more complicated... I know the chip may be driven by a crystal instead for an oscillator. These pins it can accept low levels too. So as it works this stage of the chip in the player systems. But is different in the HA-1... And is about the same chip ES9018...

Well, keep searching...:)
 
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It is (should) not be any special in this area, but I have noticed that the chip behave a little bit different, than in other configurations. The same way I used to adapt its trigger range for the clock signal on this input pin, does not work this time... It does not accept low levels signals as the other similar chips do in (f. ex.) players, and this one in HA-1 it seems more sensible to the clock signal level, than other (same) chips... It seems strange... So my conclusions that it may be some sort of software set up, or a possibility to chose between some parameters for this input...

As I wrote above: keep searching...
 
Bunpei, may I repeat the question posted a few lines above, and address it to you? Thanks.
What does pseudo- and true-differential output mean if applied to the Sabre? Hope you do know.
If to speak of traditional definition of these terms, the I/U converter scheme must be quite different for each.

Hi, cu6apum!

I hesitated to show my further explanation here because I got aware that my basic understanding on an analog DAC section of ES9018 Sabre32 architecture had been wrong at the timing of my initial posting you quoted. As of now, I have no suitable environment to check the validity of my current idea shown as below. Therefore, please remember that the following explanation is just my "guess".


1. Definitions of "True-differential" and "Pseudo-differential"

I have no idea on strict and generic meanings of those terms. I think it's better for us to regard these terms are "ES9018" specific ones.


2. Consideration on a hidden register setting for "quantizer bit length" of analog DAC section of ES9018

As the most of you may know, one channel of ES9018 has a pair of analog DAC sections, one for a positive phase and another for a negative phase. Each analog DAC section includes 64 CMOS 1 bit switches in parallel and decodes 65 level delta-sigma modulated digital signal in an unary (thermometer) coding. The switching frequency is MCLK/64. Each analog DAC section outputs a mono directional positive voltage or a negative current (outbound current from DAC chip) with 1/2 full scale off-set value.
If you think of both positive phase and negative phase output of a pair of analog DAC section, both signals are mono directional positive voltage signals. By treating the positive phase signal and the negative phase signal in a differential, we can get a bidirectional swing on one channel.

The ES9018 architecture provides an optional method for configuring its analog DAC sections so that they may accept delta-sigma modulated digital signals of higher levels, 129 (7bit), 257(8bit) and 513(9bit). (This n-bit notation is called as "quantizer bit length". It shows a level of delta-sigma modulator output.)

I illustrated these configurations in the attached figure.


3. "Pseudo differential" for "9 bit quantizer bit length" configuration

The ES9018 architecture might have a certain kind of "physical isolation" (not a galvanic isolation) between a left side (Ch1,3,5,7 side) and a right side (Ch2,4,6,8). In the case of 9 bit quantizer bit length, making 8 positive phase analog DAC sections into one group across the sides must be impossible. Therefore, 4 positive phase analog DAC sections and 4 negative phase analog DAC sections in a left side should be grouped into one positive phase output set. In the same manner, 4 positive phase analog DAC sections and 4 negative phase analog DAC sections in a right side into one negative phase output.

I think this irregular configuration is called as "Pseudo differential".

I really welcome any comments from you.

Bunpei
 

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Bunpei, thank you, this looks like the most comprehensive hypothesis made in this thread.
Yet I don't understand completely how the outputs are internally grouped together, as the physical stereo-mode design suggests simply paralleling all the outputs of each side together. This means that equal current (read: digital value) is going to be fed to all of them. Or not?!
If so, this is proven to be true for "true differential", whatever it means. And some experiments above in the thread say that if "pseudo" is chosen with polarity flip, the output signals do NOT completely cancel each other. This is more like roaming in the dark, than having a clear ideology of this chip.
And finally, on your drawing. I was pretty sure that 9-bit depth does not mean all-mono mode, it just denies "true differential". Am I wrong? Post #35, http://www.diyaudio.com/forums/digi...re-reference-dac-8-channel-4.html#post1429418

Thank you!
 
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Hi, cu6apum!

I think one of major advantages of true-differential configuration is that the total number of CMOS switches in "ON" state at one side of DAC chip is always kept constant. This is a very good requirement for an analog power supply.
As you pointed in your post, this advantage might not be obtained in the "Pseudo-differential" configuration I assumed.
However, designers of the DAC chip might have been attracted to the fantastic idea of realizing "513 level" analog DAC section accommodating 513 level delta-sigma modulated digital signal. This would be expected to bring an extremely high resolution. At the same time, the 9 bit quantizer mode should break a good symmetry built in this architecture.

As a matter of fact, I have never tried the 9 bit quantizer mode in my environment.
I appreciate comments by those who actually tried this.

Bunpei
 
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