ESS Sabre Reference DAC (8-channel)

[Russ White]

Originally posted by Terry Demol


Hi Dustin,

Very impressive work.

Can you divulge what the OP impedance of each DAC is?

This is important, for example, when choosing a suitable I-V opamp
or discrete architecture as lower Z means higher effective gain,
especially in 2 ch mode where all the OP Z's will be in parallel. The
I-V 'virtual' gain can end up being significant. This will also affect
the linearity of the I-V.

Thanks,

Terry

From the white paper.

The default configuration, in eight channel mode, is that a
pair of six bit DACs operating in anti-phase make up each
channel. Since the DACs are as described, namely a Thevenin
equivalent to a voltage source linearly between AGnd and
AVcc having an approximately 800Ω output impedance, you
may choose to connect this output to a voltage mode (noninverting
amplifier) configuration; or you may choose to
connect it to a virtual ground current mode (inverting
amplifier) configuration. The highest performance in terms of
THD is via the current mode16, but both voltage and current
mode provide about the same DNR.

The default configuration for Stereo mode, and the only
configuration that can use the SPDIF input, is to wire four
output channels in parallel. When Stereo mode is enabled in
the configuration registers the same data is sent to all four
channels. Effectively now the DACs become a pair of eight bit
DACs having an output impedance of about 200Ω. This
configuration allows >132dB of DNR to be typically
reached17. THD in the Stereo current mode is limited by the
external components and measurement equipment. We
recommend using an extremely good op-amp for the highest
performance but even an excellent op-amp is the limiting
factor in the THD18.

[rossl]

Originally posted by Russ White
Hi Ross,

I will actually probably use a PIC24 type device on my board simply because I am most familiar with it, and it has built in I2C and SPI peripherals.

Hi Russ

I ordered some PIC16F677 parts. They should be here tomorrow or Friday. That looked to be the smallest and cheapest one that has a MSSP controller for I2C.

[Dougie085]

Russ, Does your PCB you've laid out so far use SMT?

[Russ White]

Originally posted by Dougie085
Russ, Does your PCB you've laid out so far use SMT?

Yes, its essentially the same style layout as our current versions of the Opus and COD DACs. It will be the same form factor.

It will have a basic on board controller which can be disabled in favor of external control.

Common configuration changes will be made via tri-state switches.

For reference, here is the current Opus:



Cheers!
Russ

[Russ White]

Ok so if I am reading the datasheet correctly, if you want to support 192/24 spdif input you will need at least a 74.112mhz clock.

I like to use the Crystek C33xx the closest I can find is 75mhz, but I wonder if 80 or 100mhz would work better. They are great XOs.

What do you recommend Dustin?

[Dougie085]

Awesome the Opus is very nice

[Russ White]

ok to answer my own question it look like the minimum MCLK cycle time is 13ns.

1/13E-9 is 76.923Mhz

So a 75mhz XO "should" work and allow 192khz SPDIF I think....

Well I will await Dustin's response.

Cheers!
Russ

[Dougie085]

Russ are you thinking you guys might offer this as a kit or just thinking of the PCB for the most part? I'm guessing that depends on how much you like it.

[Russ White]

It would be a complete module, like the Opus. But would sell bare PCBs too.

Cheers!
Russ

[BrianDonegan]

If we do sell a kit, it would most likely come with the chips permounted. There is also the question of programming the uC.