Yes I have datas
But I am talking about the ES9008 model...
I know I need the PIC to manage registers
That is why i am asking for direction in that way
first is to set ADDR pin to gnd for L (0x90 chip address) and to +3.3Vdd for R (0x92 chip address)
EVEN this info is NOT clearly presented in the datas of ES9008
There is no word about mono operation in PDF of ES9008
as I know?
Maybe I am wrong, that is why i want to share this...
.
If You know how to set ES9008 please post this
But I am talking about the ES9008 model...
I know I need the PIC to manage registers
That is why i am asking for direction in that way
first is to set ADDR pin to gnd for L (0x90 chip address) and to +3.3Vdd for R (0x92 chip address)
EVEN this info is NOT clearly presented in the datas of ES9008
There is no word about mono operation in PDF of ES9008
as I know?
Maybe I am wrong, that is why i want to share this...
.
If You know how to set ES9008 please post this
Not much are clearly presented in the Sabre data sheets.
Thus I have made my own data sheet and added those functions that are undocumented, those explained by Dustin. And I have also added those I have figured out by test and trial.
However the ES9008 and ES9018 are pin compatible and the ES9018 can be run in ES9008 mode. The ES9018 had some fixes that was not completely correct in the ES9008 (have still a lot of ES9008 chips I did not solder due to these "bugs") the SPDIF mux was added and I think the mono mode also was one of the added features of the ES9018.
But as you have I2S the splitter you can run dual mono anyway.
Yes the 2 of the same ES9008 dac boxes are running already in dual mono
BUT i would like to get rid of the hardware logic L/L R/R
and employ classic I2S bus
.
I doubt that the people from ESS tested the dac with splitted I2S really?
And after that mark the results?
It is not lightly at all, for me?
.
So there must be a way to accomplish this with standard I2S, but
managing some registers to acheive this?
BUT i would like to get rid of the hardware logic L/L R/R
and employ classic I2S bus
.
I doubt that the people from ESS tested the dac with splitted I2S really?
And after that mark the results?
It is not lightly at all, for me?
.
So there must be a way to accomplish this with standard I2S, but
managing some registers to acheive this?
I think opposite, sorry
the great probability that mono mode is present.
BUT ESS didnt explained in the datas for ES9008 model?
ONLY the mesurements info that confirmed that it is tested in mono mode...
...
Other Qiestion is what is the mono mode exactly was?
there is a few ways to acheive this
...
1. mono mode - when I2S L/R present on the input
each dac converting only one channel, while during the other chanel converting by other dac, Resting, for the one half of L/R latch, or WS.
that is most lightly for new model and for 9008 if it comes that it is possibile to run
...
2. Spitted I2S into 2 lines L/L + R/R going into 2 x DAC chips, chips are occupied all of the time just like playng 2 x standard I2S, exept they dont know it...ha...ha
...
3. Splitted lines with zeroes L/0 + 0/R, simulated stopped sys clk opperation
...
So nothing of that was not explained clearly
I can conclude that ES9008 have possibility to run in dual mono mode
which one I can not tell?
And RayCtech also confirmed that.
Probably the one with a standard I2S L/R
but set internally via PIC controlling the registers...
?
the great probability that mono mode is present.
BUT ESS didnt explained in the datas for ES9008 model?
ONLY the mesurements info that confirmed that it is tested in mono mode...
...
Other Qiestion is what is the mono mode exactly was?
there is a few ways to acheive this
...
1. mono mode - when I2S L/R present on the input
each dac converting only one channel, while during the other chanel converting by other dac, Resting, for the one half of L/R latch, or WS.
that is most lightly for new model and for 9008 if it comes that it is possibile to run
...
2. Spitted I2S into 2 lines L/L + R/R going into 2 x DAC chips, chips are occupied all of the time just like playng 2 x standard I2S, exept they dont know it...ha...ha
...
3. Splitted lines with zeroes L/0 + 0/R, simulated stopped sys clk opperation
...
So nothing of that was not explained clearly
I can conclude that ES9008 have possibility to run in dual mono mode
which one I can not tell?
And RayCtech also confirmed that.
Probably the one with a standard I2S L/R
but set internally via PIC controlling the registers...
?
Ok, go through old Dustin Forman post and you will get your answer.
But perhaps it did not know the ES9018 very well ....
Mono mode is just a shortcut to bypass your L+L/R+R or what ever you want I2S reformatting.
I dont't understand your interrogation about I2S clocking VS DAC conversion. The conversion is done on frame boundary. When the DAC look for L or R or L+R samples, sample are there with no time dependent ordering, it is the job of the I2S receiver stage.
But perhaps it did not know the ES9018 very well ....
Mono mode is just a shortcut to bypass your L+L/R+R or what ever you want I2S reformatting.
I dont't understand your interrogation about I2S clocking VS DAC conversion. The conversion is done on frame boundary. When the DAC look for L or R or L+R samples, sample are there with no time dependent ordering, it is the job of the I2S receiver stage.
.
But Is that only way?
Because it is just an "external" way
forcing ES9008 to play channels independently?
it is simple
everything is the same like standsrd I2S
WS goes to change state one cycle prior to the MSB on every word start
SYS CLK is normal.
The content of the word L or R is the same...
everything is the same
Just order of the words are exchanged
Standard I2S have L following R word, and after that booth going to conversion
DAC does not mind what the content of the words or what word comes first or after that, Dac minds just that the bus following the protocol, and if it is in mutual synchronisation like it should be...
Info given by Dustin to Russ White when the 9018 goes out:
http://www.diyaudio.com/forums/twisted-pear/128137-buffalo-dac-ess-sabre-9008-a-126.html#post1707811
And don't get me wrong : all what I am saying is that native mono mode was a 9018 addition and does not exist on 9008 even if you could obtain the same result with external I2S pre-processing.
http://www.diyaudio.com/forums/twisted-pear/128137-buffalo-dac-ess-sabre-9008-a-126.html#post1707811
And don't get me wrong : all what I am saying is that native mono mode was a 9018 addition and does not exist on 9008 even if you could obtain the same result with external I2S pre-processing.
Effect of DPLL Bandwidth Parameter
I assume that the number of ES9018 based DAC users those who have tried a synchronous master clocking method is increasing. With the method we are almost free from the disastrous ES9018 specific "unlock" events even when we select "the lowest" bandwidth for 384kHz/32bit PCM I2S.
By the way, has anyone observed a DPLL bandwidth parameter dependence of variability of DPLL counter value under a constant synchronous master clocking condition?
The reason why I ask about it is that I have no good understanding on the role of "DPLL bandwidth" parameter.
Even under a synchronous master clocking scheme that Russ once described it somewhere as "DPLL is free-wheeling", there are slight value changes in a DPLL counter. Does the wider DPLL bandwidth parameter cause the larger fluctuation of DPLL counter value?
I assume that the number of ES9018 based DAC users those who have tried a synchronous master clocking method is increasing. With the method we are almost free from the disastrous ES9018 specific "unlock" events even when we select "the lowest" bandwidth for 384kHz/32bit PCM I2S.
By the way, has anyone observed a DPLL bandwidth parameter dependence of variability of DPLL counter value under a constant synchronous master clocking condition?
The reason why I ask about it is that I have no good understanding on the role of "DPLL bandwidth" parameter.
Even under a synchronous master clocking scheme that Russ once described it somewhere as "DPLL is free-wheeling", there are slight value changes in a DPLL counter. Does the wider DPLL bandwidth parameter cause the larger fluctuation of DPLL counter value?
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Depends on your transport, especially if accepts external clock. What do you have as I2S source?
I agree with roender's view point.
There are three approaches on the allocation of master clock sources.
1. At a DAC side
acko's "Turbo Clock", Chiaki's sync-clock-DAC
Divided clock signals are sent back to a transport side.
2. At FIFO buffer inserted between a transport and a DAC
Ian's FIFO, FIFO designed by Mr. Kakuta of AIT LABO ( in Japan)
3. At a transport side
Chikai's SDTrans, Multiplier & jitter cleaner designed by Mr. Fujiwara (in Japan)
Multiplied clock signals are sent forward to a DAC side from a transport side.
In all the cases, you must prepare good clock generators.
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PC sound card proccesor.
I consider waiting for multich 32bit USB-I2S DSD transport, in this regard I guess third approach will be better one?
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+1.2V power for ES9018
I'm sorry that I have not checked whether it is a FAQ or somewhere it is explained.
There are 7 power pins on ES9018 for +1.2V power;
1 VDD_L Analog Power(+1.2V) for Left channels
16 VDD_L Analog Power(+1.2V) for Left channels
20 VDD Digital Power(+1.2V) for core of chip
29 VDD Digital Power(+1.2V) for core of chip
33 VDD_R Analog Power(+1.2V) for Right channels
48 VDD_R Analog Power(+1.2V) for Right channels
61 VDD Digital Power(+1.2V) for core of chip
I understand that "Analog Power" means "related to analog DAC section" of the chip and "Digital Power" means "related to digital processing core section" and all power lines are connect to internal digital circuits.
Does any one have any clear empirical result that it's better for us to assign separate +1.2V regulators for "Analog Power" and "Digital Power" respectively?
I found acko's DAC board provides separate power input terminals.
I'm sorry that I have not checked whether it is a FAQ or somewhere it is explained.
There are 7 power pins on ES9018 for +1.2V power;
1 VDD_L Analog Power(+1.2V) for Left channels
16 VDD_L Analog Power(+1.2V) for Left channels
20 VDD Digital Power(+1.2V) for core of chip
29 VDD Digital Power(+1.2V) for core of chip
33 VDD_R Analog Power(+1.2V) for Right channels
48 VDD_R Analog Power(+1.2V) for Right channels
61 VDD Digital Power(+1.2V) for core of chip
I understand that "Analog Power" means "related to analog DAC section" of the chip and "Digital Power" means "related to digital processing core section" and all power lines are connect to internal digital circuits.
Does any one have any clear empirical result that it's better for us to assign separate +1.2V regulators for "Analog Power" and "Digital Power" respectively?
I found acko's DAC board provides separate power input terminals.
This is an old post belonging to Russ White:
"All that the 1.2V supplies are used for (beside the core 1.2V) to drive the level shifters for the analog stage.
They do not need to be and there is no benefit from (in any measurable way according to Dustin) them having supplies that are separate from the core 1.2V supply.
Now some here may feel compelled to provide a separately regulated supply for the level shift drivers, but practically I can't find a good reason to do it. If Dustin says don't bother, I say I won't. So I didn't. I drive the level shifters from the same 1.2 volt regulator as the core uses."
"All that the 1.2V supplies are used for (beside the core 1.2V) to drive the level shifters for the analog stage.
They do not need to be and there is no benefit from (in any measurable way according to Dustin) them having supplies that are separate from the core 1.2V supply.
Now some here may feel compelled to provide a separately regulated supply for the level shift drivers, but practically I can't find a good reason to do it. If Dustin says don't bother, I say I won't. So I didn't. I drive the level shifters from the same 1.2 volt regulator as the core uses."