Simple FIFO to I2S CPLD, for MCU players / reclocking

[KOON3876]

I used dsPIC at "Ultimate Source" project,
ultimate source
Then I could make small WAV file player working with genuine 11.288MHz/44.1kHz/16bit.

But I'm not satisfied because it is straitjacketed to dsPIC.
I searched threads and google to look for simple I2S generator, but can't find (I'm not good at google?).

Attached is veeery simplified I2S generator.
It only needs 8 bit width FIFO, CPLD, and 11.288MHz.

Principle "no wisdom / foolish simple"
(1) 6bit counter, generates 64 states. (same as I2S 64clock/frame)
States are L01-L32,R33-R64.
(2) CPLD generates READ# pulse when FIFO is ready, at state R45,47,49,51. store data to registers.
When FIFO is not ready, Registers filled with 0x00.
(3) CPLD outputs LRCK, SCK, SD.
SD is selected from register bit, by state.
So if data is ready, it generates 44.1kHz/16bit I2S signal, and data is not available, just generates 0000000 I2S.

Requirement for MCU
It has some "receiving" interface > 176.4KB/s.
It can write FIFO, 8bit parralel, at least > 176.4KB/s. order is Left lower, Left Upper, Right lower, Right Upper.
Byte Order is same as WAV file format.

Requirement for FIFO: almost nothing. just 8 bit or more, 4 word or more.

I will post VHDL code if it works. (will be tested by FTDI FT245R)

[KOON3876]

Attached contains schematic and Board image.

[KOON3876]

very long time no see, VHDL.
On simulation it looks like generating correct LRCK/SCK/SD.
Can anyone inspect / simulate attached bush-league code?

[blu_line]

One remark.
RST is an active low signal. Call it RSTN or RST_N to make this known to others.

RTL simulation is correct !

Would you like to have the TB ?

What about post place and route ?

grtz

Simon

[KOON3876]

Thank you for responce. here is mapping result. what is TB?

Device Used: XC9572-10-PC44
Fitting Status: Successful

************************* Mapped Resource Summary **************************

Macrocells,Product Terms,Block,Registers,Pins
Used/Tot,Used/Tot,Used/Tot,Used/Tot,Used/Tot
49 /72 ( 68%),113 /360 ( 31%),108/144 ( 75%),42 /72 ( 58%), 15 /34 ( 44%)

[rfbrw]

Testbench

So what exactly is this thing supposed to do ?

[KOON3876]

Attached contains current VHD, UCF, TestBench, Report.
(ISE Simulator)

>blu_line
Maybe you have better test-bench than me!

>rfbrw
this thing does "FIFO to I2S" that's all.
I can not find this kind of simple device in diyaudio / google (maybe already exists but I can not find).

this thing simplify digital audio playback.
almost any micro processer can be used for audio playback.
Linux player just send FIFO and forget, to play music.
DAC DIYer can make re-clocking easy.

application, with accurate I2S output
small hard-disk player
yet another AirPort Express / squeezebox
handy SD-Card player
USB FIFO(FT245R) Playback device (I will try it)

[rfbrw]

I take it you feed it 8 bit words at a certain rate and it creates 16 bit left and right audio data.

[KOON3876]

Board, Parts were already ordered. maybe I can try this weekend or next.

[KOON3876]

Wave shows SD and LRCK. I think it is working like I thought, and lower photo, CS4334 test dac is playing Bach.
(wave form is not clean, LRCK is gated or output / not latched. maybe LRCK/SCK/SD should be re-sampled..)

I wrote simple sample source (read wav / send blocks to FIFO) and there are still noize, by FIFO underrun. I will think later.

Anyone please try same way with more powerful device.
I think Cypress EZ-FX2 (480Mbps) and larger CPLD can play 24/192, 4-way data for multi-amplifier. much cheaper than RME/Lynx.