One clock for CDM12 Pro2 and Nos Dac TDA1545 - diyAudio
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Old 18th October 2007, 11:52 AM   #1
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Default One clock for CDM12 Pro2 and Nos Dac TDA1545

Hello

I plan to feed my TDA1545 nos dac direct with eiaj from my cdm12pro2 drive. And here is my problem. Can I feed the drive (clock is 8.4672 MHz) and the TDA1545 in NOS Mode from the same clock?
Maybe use the synchronous reclocking like the swenson schematic published on slimdevices.
I will use a Tent XO

Thank you for help

Toni
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Old 19th October 2007, 02:04 PM   #3
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Is better clock in the CDM12 Pro2 an improovment when I use it at drive only, or for the internal dac?
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Old 21st October 2007, 01:06 AM   #4
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Quote:
Originally posted by gochtoni_toni
I plan to feed my TDA1545 nos dac direct with eiaj from my cdm12pro2 drive. And here is my problem. Can I feed the drive (clock is 8.4672 MHz) and the TDA1545 in NOS Mode from the same clock?
Maybe use the synchronous reclocking like the swenson schematic published on slimdevices.
I will use a Tent XO
Exactly how do you plan to drive the TDA1545 with 8.4672MHz? Typical bit clock for a NOS DAC is 2.8224, 2.1168, or 1.4112 MHz, depending on the frame size.

What’s the purpose of reclocking? The clock outputs from the CDT are derived by dividing the master oscillator using a synchronous counter. A counter is nothing but a collection of latches that are all clocked by the master oscillator. So, if the clocks are the output of a latch clocked by the master oscillator, what is gained by reclocking them with yet another latch clocked by the master oscillator?

The data bits are collected from the CD and assembled in a shift register, which is clocked by the bit clock. A shift register is also a collection of latches and the destination of the data bits is a shift register inside the DAC chip. So, what is gained by reclocking the data bits in between two sets of shift registers (latches); all clocked by the same clock?

The only thing you are likely to gain by reclocking is more jitter, not less? Look at this implementation, for example. Synchronous Reclocker. Feedback please
Here the oscillator is driving at least four loads and significant additional trace and wire length. Most oscillators are spec’d for no more than three loads and they perform best with one load and very short traces. More loads and trace length increases the capacitance of the circuit, which slows down the signal transitions. Slow transitions increase the uncertainty as to when the transition crosses the binary threshold and is recognized by the receiving circuit. That results in more jitter. I find it amusing that in your quest to reduce jitter, most of you actually increase it with reclocking.
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Old 21st October 2007, 01:27 AM   #5
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The received wisdom is that the bitclock signal generated as part of the I2S output of the SAA7324 is a jittter-prone signal, utterly corrupted by the louche activities taking place around it. By contrast, the output of a '163 or a pair of picogate flip-flops is beyond reproach. Or so I am told.
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Old 24th October 2007, 11:38 AM   #6
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Hello

I will use this schematic, its published by John Swenson on slimdevices forum to make synchronous reclocking between a SB3 and an nos dac. I will use 11.xxx mHz on the dac and 33.xxx mHz at the drive. Swenson use a 74hcu04 to fed the clock si´gnal back to the drive. What logic I must use to multiply the 11.xxxmhz to 33.xxxmhz.

Here is the schematic
Attached Images
File Type: jpg sb3%20clock%20layout%20v6.jpg (96.0 KB, 714 views)
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Old 24th October 2007, 11:38 AM   #7
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Link to the schematic


http://home.comcast.net/~johnswenson1/stereo/SBI2S.gif
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Old 28th October 2007, 03:22 AM   #8
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Toni,
The CDM12 Pro2 drive puts out I2S in default mode. You'll need to configure the CDM12 Pro2 to put out EIAJ format that the TDA1545 recognise.
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Old 28th October 2007, 03:45 AM   #9
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Quote:
Originally posted by gochtoni_toni
Hello

I will use this schematic, its published by John Swenson on slimdevices forum to make synchronous reclocking between a SB3 and an nos dac. I will use 11.xxx mHz on the dac and 33.xxx mHz at the drive. Swenson use a 74hcu04 to fed the clock si´gnal back to the drive. What logic I must use to multiply the 11.xxxmhz to 33.xxxmhz.

Here is the schematic

Where exactly on the dac do you plan to send 11MHz ?
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Old 29th October 2007, 06:08 AM   #10
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Hello VT4C

I have the controller, you designt for Diyparadise.


I will recklock the bitclock with 11.xxxmHz
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