QSerraTico_Tico said:
The issue of which Philips TDA DAC chip accepting certain input formats is confusing. Here, e.g., are two posts mixed with (=conflicting) opinions on Philips TDA chips and the input formats each potentially accepts (I think the poorly-worded language in the datasheets are mostly to blame):
http://www.pinkfishmedia.net/forum/showpost.php?p=485918&postcount=2
http://www.diyaudio.com/forums/showthread.php?threadid=58564
Anyone care to take a stab:
TDA1543
TDA1543A
TDA1545
TDA1545A
TDA1541
TDA1541A
How I do lament the passing of the good old days when you had to at least have a passing acquaintance with the topic at hand before you were allowed even a sniff of a datasheet not least because they came in 1000 page tomes and you had to ask for them. That everyone and his dog is allowed access these days does not change the fact that these are specialist publications and some prior knowledge is assumed. Perhaps next time I feel a little discomfort and wish to self-diagnose I should go wailing to the medical authorities about the excessive use of latin and compound words in their texts.
Toni,
The board layout in your post #6 is my implementation of John's schematic. John would have, undoubtedly, built it better.
For this implementation, the master clock (on this board) sits in the DAC box proximate to the dac input pins. It sends the master clock back to the transport; in this case a squeezebox 2. The SB2 outputs left justified format, not I2S. Hence, there is add'l complexity on the board you referenced (unnecessary for those with transports that output i2s) to convert the left justified format to i2s, because my dac tda1541 is able to input i2s, not left justified format. Once the signal is received by the dac box, it is converted to i2s and re-synched by the same master clock. Jitter at the dac pins is essentially the jitter on the output of the clock--in my case a Tent clock which is spec'd at under 3ps. The frequency is 11.2896 for both dac and transport, everything is synchronous. It sounds wonderful and transformed my dac. As you can see, this circuit is pretty specialized. For more details I created a simple website mainly for squeezebox users (below). I'm not familiar with the tda1545 chip and its permutations.
http://home.socal.rr.com/audio_gestalt/default.htm
The board layout in your post #6 is my implementation of John's schematic. John would have, undoubtedly, built it better.
For this implementation, the master clock (on this board) sits in the DAC box proximate to the dac input pins. It sends the master clock back to the transport; in this case a squeezebox 2. The SB2 outputs left justified format, not I2S. Hence, there is add'l complexity on the board you referenced (unnecessary for those with transports that output i2s) to convert the left justified format to i2s, because my dac tda1541 is able to input i2s, not left justified format. Once the signal is received by the dac box, it is converted to i2s and re-synched by the same master clock. Jitter at the dac pins is essentially the jitter on the output of the clock--in my case a Tent clock which is spec'd at under 3ps. The frequency is 11.2896 for both dac and transport, everything is synchronous. It sounds wonderful and transformed my dac. As you can see, this circuit is pretty specialized. For more details I created a simple website mainly for squeezebox users (below). I'm not familiar with the tda1545 chip and its permutations.
http://home.socal.rr.com/audio_gestalt/default.htm
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