Left-justified I2S to Philips I2S Converter - diyAudio
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Old 30th April 2007, 12:43 AM   #1
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Default Left-justified I2S to Philips I2S Converter

I would like to convert from left-justified I2S to an I2S format compatible with TDA1541A(let's call it Philips I2S)
Please see this datasheet, page 6:
http://www.analog.com/UploadedFiles/...ets/AD1852.pdf
(conversion from the format in figure 3 to the format in figure 2)

The question is whether the attached schematic would do it in a problem free manner. Also, does anyone in here prefer some manufacturers over the others when it comes to these logic chips?
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Old 30th April 2007, 12:49 PM   #2
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You should check the timing relationship between BCLK and DATA.

You should also consider setup and hold time of 74hc164 and compare that with the source signal. See attached image and refer to datasheet of your 74hc164 for the limit of Tsu and Th.
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Old 30th April 2007, 12:57 PM   #3
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I looked at the ad1852 datasheet in the link you posted. DATA is valid during rising edge of BCLK. However the DATA output from 74hc164 is slightly delayed after rising edge BCLK. This is mentioned in the datasheet of 74hc164.
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Old 30th April 2007, 03:52 PM   #4
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Quantran, thanks for replying.
What would you recommend in this situation?
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Old 30th April 2007, 03:58 PM   #5
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Default Shifter

http://www.geocities.com/nonospcm170...l_shifter.html

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Old 30th April 2007, 05:12 PM   #6
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You may try this. I think this should work but I can't guarantee.
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Old 30th April 2007, 05:33 PM   #7
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So what about this? Double inverting for delay than flip flop
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Old 30th April 2007, 07:05 PM   #8
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Tico, that circuit is very complex, it's also meant for mono DAC chips like the 1704.
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Old 1st May 2007, 07:53 AM   #9
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I don't think this is a good solution.

Quote:
Originally posted by curva
So what about this? Double inverting for delay than flip flop
How much delay would you expect from 74hc4d and 74hc4e? I see no effect in addition 74hc4d and 74hc4e before 74hc74.

You still have the same problem of timing relationship between SDATA out and BCLK. 1Q is updated right after rising edge of BCLK. This mean that DATA out is only valid after rising edge of BCLK. Your desired format require that rising edge of BCLK is somewhere around the middle of DATA.

To deal with this problem, you may see that I recommended to invert BCLK for the 2nd half of 74HC74 in the schematic. Each half of the 74hc74 cause a delay of 1/2 BCLK cycle. I am pretty sure about the logic but I have not tried it therefore ...
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Old 1st May 2007, 08:34 AM   #10
Valerii is offline Valerii  Ukraine
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Default philips I2s

Hello.
It is the working circuit, I connected her(it) to Philips-930.
Saa7310+sm5813+ad1865
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