How many modulation methods in Class D amplifier ?

[dusfor99]

Originally posted by Pafi


This is not true. Timing error caused by fall and rise time depends on output current in a nonlinear way, no matter PWM or sigma/delta.

Pafi,

While true that there is a non-linear dependence of the rise and fall times with output current (which I believe is affected by the amount of dead-time you put into the output driver) This affect is secondary to the error caused by having a delta sigma scheme in which the switching frequency is related to the output amplitude.

Let me know what you think. Im open to all criticism.


CLD

[Pafi]

dusfor99!

Sorry, I haven't red your statement carefully. Now I've done. You are partly right, there is an effect causes distortion due voltage dependent frequency, but in practice this is typically a very weak effect compared to others (eg. effect of dead time), arises only at really high output voltage, generates only low order harmonics, and can be reduced effectively by a very simple computing in digital domain.

I thought you were talking about one of the main reasons of distortion: dead time induced distortion, wich arises at low level, generates high order harmonics, and cannot be predicted (so cannot be reduced) based on input signal. This distortion arises at every kind of modulation.

BTW: you seem to use different definitions as usual. Please check attached file!

The error you referred to doesn't only depend on rise and fall times, but on difference of delay times too.

[dusfor99]

The error you referred to doesn't only depend on rise and fall times, but on difference of delay times too.

Yes, I totally agree.


So the main contributer to THD is actually the dead-time that is introduced to that there is no "shoot-through" current in the output drivers? I have done some spice simulations showing that the more dead-time between the Nmos and Pmos the more dependece of the output switching speed (whether it be rise/fall, dead-time...) with the load current. One more thing that I suspect (but havent taken a close look into yet) is the mismatch in R-on of the pull-up and pull-down FET's causing THD due to the output impedance changing with output level. Do you have any insight on this area?

Thanks

CLD

[Pafi]

I have done some spice simulations showing that the more dead-time between the Nmos and Pmos the more dependece of the output switching speed

I'd rather call it switching delay.

Do you use complementary output? It's not typical, however I build some too like this.

One more thing that I suspect (but havent taken a close look into yet) is the mismatch in R-on of the pull-up and pull-down FET's causing THD due to the output impedance changing with output level.

Yes, this can be proved by simulation easily, but fortunately this is usually a small, and not too disturbing (2nd order) distortion again.

[dusfor99]

Hi Pafi,

What kind of output stage do you reconmend? A dual N-mos with a bootstrapping circuit to drive the high side? My main experience is in creating the PWM modulator itself, an not too much on the most important part of all, the analog output drivers, but that is an area I wnat to venture into.


CLD

[Pafi]

I can't recommend any. There are advantages and disadvantages of both. Generally n+n is better (more simmetric, have lower loss, etc...), n+p is simpler (a little).

[xuhaoz]

Hi, reading your discussions is a good way to learn knowledge, although I do not quite understand :-). But I will keep learning.

During these days, from the articles I have read, I found self-oscillating modulator(hysteresis, phase-shift) is more popular than other methods, and phase-shift controlled self-oscillating modulator seems better, could you please tell me why it is called phase-shift ? or maybe you can explain this in more details or in another way. Thanks a lot.

Regards
Jimmy

[dusfor99]

Originally posted by xuhaoz
Hi, reading your discussions is a good way to learn knowledge, although I do not quite understand :-). But I will keep learning.

During these days, from the articles I have read, I found self-oscillating modulator(hysteresis, phase-shift) is more popular than other methods, and phase-shift controlled self-oscillating modulator seems better, could you please tell me why it is called phase-shift ? or maybe you can explain this in more details or in another way. Thanks a lot.

Regards
Jimmy

Hi Jimmy,

Ok, I dont have any experience with the self oscillating designs, but I think I have a handle on how they work. Its linked very closely to control theory. Where basically if you have a negative feedback loop that accumulates 180 degrees of phase shift for any given frequncy, the gain at that frequncy better be well below 0dB or the loop will ocsillate. Google "gain and phase margin" to read up on this. Its called "phase-shift" because there is some time delay from the input to the output of the modulator. A phase shift is just that, a time delay calculated as a fraction of the period of the frequncy your talking about. For example, a 1kHz tone has a period of 1ms, if you were to delay that tone by 0.5ms that would be 180degress of phase shift. The formula is

Phase_Shift = 360*(Td*F)

where Td = time delay, and F = frequency

Like before 180 = 360*(.5e-3*(1/1e3))



The self oscillating class-D amps PURPOSELY get set in oscillation and that oscillation is the drive signal to the ouptut MOSFET's. Imagine this is how is works.

Say you have a loop that has a phase shift of 180degree's @ 500kHz, and it has some gain at 500kHz aswell. Then if you put in even the tiniest amount of signal at 500kHz (even the background noise of the system at 500kHz) will cause the look to oscillate. It goes like this. If the input goes up, then the output goes down (due to 180 degree's phase shift) since you have NEGATIVE feedback, the loop will see the UP - DOWN = a bigger UP, the the vicious cycle starts again. Thats a very oversimplified explanation, but it should get you started.


CLD

[Andrew Eckhardt]

Thats a very oversimplified explanation, but it should get you started.


CLD [/B][/QUOTE]


Here is a circuit that works to explain a self oscillating PWM. It's the first PWM I ever built, although I did that in 1989. I think this circuit is older than 1978.

[dusfor99]

Hi Andrew,

I cant seem to find the link to the circuit you did. Im interested in reading about it though.


THanks


CLD