UcD output stage current sensing

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I have thought up an idea of lossless Ids measurement (for overcurrent protection), presented in http://zilog.dyndns.org:8080/lagenheten/lossless_Ids.png, would this work in reality? I want to use the classic UcD style gate drivers, therefore I have designed it this way, the BJT across Vsense is to clamp to lower rail at main FET turn-off, where the sensing FET tends to turn on through the miller capacitance.

I guess I need to use an RC filter to eliminate ringing in Vsense. I guess I also could clamp Vsense for longer time since the pulse width of an UcD is longer during overcurrent, and this gives me longer time to react before the pulse is gone.
 
Gorilla said:
I think I understand what your trying to do, soo...

If your scheme was implemented on a totem pole arrangement, how would your current sense detect overcurrent if both (totem pole) FETs were on?


The circuit only shows the principle for one FET, I see no reason why this could not be implemented for the top FET aswell. I would of course need to add an RC filter and a BJT that senses the overcurrent condition from each sense-circuit.
 
Hello Daniel,

I did not literally mean AND/OR "function" as LOGIC gates.... nor are you gonna use one either.... can be be done the discrete way...

sorry I cant post a scheme without violating a patent ...:xeye:

Do your sensing near the supply lines... and you should AND/OR thier outputs to -turn-OFF- the current source...


your roughy "IN" there.. simulate more...



Regards,
Raff
 
RX5 said:
Hello Daniel,

I did not literally mean AND/OR "function" as LOGIC gates.... nor are you gonna use one either.... can be be done the discrete way...

sorry I cant post a scheme without violating a patent ...:xeye:

Do your sensing near the supply lines... and you should AND/OR thier outputs to -turn-OFF- the current source...


your roughy "IN" there.. simulate more...



Regards,
Raff

You mean that I should use one sensing curcuit per half of the bridge and OR the shutdown-signals? I already do that today (using current sense resistors). Right now I am only interested in how I should sense the current through the mosfets using their voltage drop across Vds, and at the same time avoid false triggering at turn-on and turn-off edges.
 
Now I have taken the idea further (read some Q4D note and got an idea). The problem now is that LTSpice does not model these BJTs accurately, I need BJT models that take saturation into account, anybody know where to find this (as my leading edge blanking circuit depends on this phenomena) ?.

Aside from this, am I in the ballpack with the Rds(on) current sensing curcuit yet? Will it hold up when PCB stray inductance and MOSFET cross conduction in present?

http://zilog.dyndns.org:8080/lagenheten/oc_prot.png
 
RX5 said:
since your already trying to add an over_current protection, this also means you have a "sounding" UCD amp now right?:smash:

have you used op-amp buffer(input) already? ;)

keep it up!


I have a playing UcD on the table next to me, it looks like the patent with some additions for noise suppression and protection. It uses a NE5532 for input buffering, but it is outside of the UcD feedback loop. Now I am working on a more efficient and less noisy one, with better performance of the startup and protection logic.
 
RX5 said:
zilog,


post pics :D

btw, what MOSFETS did you use??


keep it up dude!! make a board so noise/EMI/RFI are at minimum.. tried double sided?? :) I can see in your past/other post that you made a different board for modulator and another for the mosfet driver!! cool!!!

Cheers,
Raff

I use Fairchild FDP3682 because of their low Qrr and easiness to drive. The board I use now is double sided, but I havent yet used the ground planes the way I should. The next version will be based on double sided PCB (most advanced I can make myself), mostly SMD components, RM-core inductor and a vertical modulator board to keep magnetic interference from the output inductor to a minimum. I am also calculating to use smaller rail capacitors to keep the size of the high current loop down.
 
Zilog,


I have DL'd the datasheet for FD3682.. hmmm nice specs.. although highvalue on -rise time-, real great with the Qrr = 92..... lowest ever for a fast switcher.. 100V 32A 36mOHM...

SMD? thats nice... mine with SMD? in my dreams :D possible but not practical for me...

about the vertical modulator, mine is too... :) so that is WHY the UCD modules are verticaly mounted...

keep it up!!


Cheers,
Raff
 
I have spiced yet another variant of OC protection, http://zilog.dyndns.org:8080/lagenheten/oc_sense.png - will this work in real life?

I have tested variants of this on breadboard, but EMI, inductance etc destroys my measurements too much to draw any conclusions yet.

The idea is to sense the voltage drop across the mosfets (eventually both low and high side mosfets), and blank the falling and rising edges which would cause erroneous measurements with the rising edges of both high and low side mosfets. Rising edge of the high side mosfet means falling edge of the low side mosfet etc.
 
zilog said:
I have test built it now, and it works!

http://zilog.dyndns.org:8080/lagenheten/oc2.jpg
http://zilog.dyndns.org:8080/lagenheten/oc3.jpg

Just need to incorporate this stuff into the trip/timing circuit to give it a real test now.. who needs sleep anyway? ;)

P.S. the waveform displayed is the inverse of Vsense_after_clamp, 200mV/div at ~5A rms load.


thats great!!


:smash:

define : now it works!... you mean you actually shorted out the speaker terminals? at what supply levels are you running your UCD?

:D
 
RX5 said:



thats great!!


:smash:

define : now it works!... you mean you actually shorted out the speaker terminals? at what supply levels are you running your UCD?

:D


Nope, this means that I can get clean spike and glitch-free Ids-measurement good enough to trip OC protection for the lower mosfet. Next step involves adding sensing for the high side mosfet and getting it to work with my timer circuit.
 
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