UcD output stage current sensing

[zilog]

I have thought up an idea of lossless Ids measurement (for overcurrent protection), presented in http://zilog.dyndns.org:8080/lagenhe...ssless_Ids.png, would this work in reality? I want to use the classic UcD style gate drivers, therefore I have designed it this way, the BJT across Vsense is to clamp to lower rail at main FET turn-off, where the sensing FET tends to turn on through the miller capacitance.

I guess I need to use an RC filter to eliminate ringing in Vsense. I guess I also could clamp Vsense for longer time since the pulse width of an UcD is longer during overcurrent, and this gives me longer time to react before the pulse is gone.

[Gorilla]

I think I understand what your trying to do, soo...

If your scheme was implemented on a totem pole arrangement, how would your current sense detect overcurrent if both (totem pole) FETs were on?

[zilog]

Originally posted by Gorilla
I think I understand what your trying to do, soo...

If your scheme was implemented on a totem pole arrangement, how would your current sense detect overcurrent if both (totem pole) FETs were on?

The circuit only shows the principle for one FET, I see no reason why this could not be implemented for the top FET aswell. I would of course need to add an RC filter and a BJT that senses the overcurrent condition from each sense-circuit.

[RX5]

do an AND/OR "function"

[zilog]

Originally posted by RX5
do an AND/OR "function"

Im sorry for asking stupid questions, but what do I acomplish doing that? Could you please also provide a circuit example as I do not know where to put this logic arrangement.

/Daniel

[RX5]

Hello Daniel,

I did not literally mean AND/OR "function" as LOGIC gates.... nor are you gonna use one either.... can be be done the discrete way...

sorry I cant post a scheme without violating a patent ...

Do your sensing near the supply lines... and you should AND/OR thier outputs to -turn-OFF- the current source...


your roughy "IN" there.. simulate more...



Regards,
Raff

[zilog]

Originally posted by RX5
Hello Daniel,

I did not literally mean AND/OR "function" as LOGIC gates.... nor are you gonna use one either.... can be be done the discrete way...

sorry I cant post a scheme without violating a patent ...

Do your sensing near the supply lines... and you should AND/OR thier outputs to -turn-OFF- the current source...


your roughy "IN" there.. simulate more...



Regards,
Raff

You mean that I should use one sensing curcuit per half of the bridge and OR the shutdown-signals? I already do that today (using current sense resistors). Right now I am only interested in how I should sense the current through the mosfets using their voltage drop across Vds, and at the same time avoid false triggering at turn-on and turn-off edges.

[RX5]

yup.. 1 sensing per rail..... AND/OR them for a single output....

I remember seing the exact formula in the philips app note... its in there...

[zilog]

Now I have taken the idea further (read some Q4D note and got an idea). The problem now is that LTSpice does not model these BJTs accurately, I need BJT models that take saturation into account, anybody know where to find this (as my leading edge blanking circuit depends on this phenomena) ?.

Aside from this, am I in the ballpack with the Rds(on) current sensing curcuit yet? Will it hold up when PCB stray inductance and MOSFET cross conduction in present?

http://zilog.dyndns.org:8080/lagenheten/oc_prot.png

[RX5]

since your already trying to add an over_current protection, this also means you have a "sounding" UCD amp now right?

have you used op-amp buffer(input) already?

keep it up!