UcD output stage current sensing

[zilog]

Originally posted by RX5
since your already trying to add an over_current protection, this also means you have a "sounding" UCD amp now right?

have you used op-amp buffer(input) already?

keep it up!

I have a playing UcD on the table next to me, it looks like the patent with some additions for noise suppression and protection. It uses a NE5532 for input buffering, but it is outside of the UcD feedback loop. Now I am working on a more efficient and less noisy one, with better performance of the startup and protection logic.

[RX5]

zilog,


post pics

btw, what MOSFETS did you use??


keep it up dude!! make a board so noise/EMI/RFI are at minimum.. tried double sided?? I can see in your past/other post that you made a different board for modulator and another for the mosfet driver!! cool!!!

Cheers,
Raff

[zilog]

Originally posted by RX5
zilog,


post pics

btw, what MOSFETS did you use??


keep it up dude!! make a board so noise/EMI/RFI are at minimum.. tried double sided?? I can see in your past/other post that you made a different board for modulator and another for the mosfet driver!! cool!!!

Cheers,
Raff

I use Fairchild FDP3682 because of their low Qrr and easiness to drive. The board I use now is double sided, but I havent yet used the ground planes the way I should. The next version will be based on double sided PCB (most advanced I can make myself), mostly SMD components, RM-core inductor and a vertical modulator board to keep magnetic interference from the output inductor to a minimum. I am also calculating to use smaller rail capacitors to keep the size of the high current loop down.

[RX5]

Zilog,


I have DL'd the datasheet for FD3682.. hmmm nice specs.. although highvalue on -rise time-, real great with the Qrr = 92..... lowest ever for a fast switcher.. 100V 32A 36mOHM...

SMD? thats nice... mine with SMD? in my dreams possible but not practical for me...

about the vertical modulator, mine is too... so that is WHY the UCD modules are verticaly mounted...

keep it up!!


Cheers,
Raff

[zilog]

I have spiced yet another variant of OC protection, http://zilog.dyndns.org:8080/lagenheten/oc_sense.png - will this work in real life?

I have tested variants of this on breadboard, but EMI, inductance etc destroys my measurements too much to draw any conclusions yet.

The idea is to sense the voltage drop across the mosfets (eventually both low and high side mosfets), and blank the falling and rising edges which would cause erroneous measurements with the rising edges of both high and low side mosfets. Rising edge of the high side mosfet means falling edge of the low side mosfet etc.

[zilog]

I have test built it now, and it works!

http://zilog.dyndns.org:8080/lagenheten/oc2.jpg
http://zilog.dyndns.org:8080/lagenheten/oc3.jpg

Just need to incorporate this stuff into the trip/timing circuit to give it a real test now.. who needs sleep anyway?

P.S. the waveform displayed is the inverse of Vsense_after_clamp, 200mV/div at ~5A rms load.

[Baldin]

Real nice going

.... here I'm trying to get a LM319 to work as a OC sensor

[RX5]

Originally posted by zilog
I have test built it now, and it works!

http://zilog.dyndns.org:8080/lagenheten/oc2.jpg
http://zilog.dyndns.org:8080/lagenheten/oc3.jpg

Just need to incorporate this stuff into the trip/timing circuit to give it a real test now.. who needs sleep anyway?

P.S. the waveform displayed is the inverse of Vsense_after_clamp, 200mV/div at ~5A rms load.

thats great!!




define : now it works!... you mean you actually shorted out the speaker terminals? at what supply levels are you running your UCD?

[zilog]

Originally posted by RX5



thats great!!




define : now it works!... you mean you actually shorted out the speaker terminals? at what supply levels are you running your UCD?

Nope, this means that I can get clean spike and glitch-free Ids-measurement good enough to trip OC protection for the lower mosfet. Next step involves adding sensing for the high side mosfet and getting it to work with my timer circuit.

[soongsc]

So this means it's also going to mimize startup transient outputs?