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Old 21st December 2002, 11:53 AM   #51
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Helo,


I am new to this forum. I have just started drawing shematics for TAS5015 based amplifier. If the design will be any good I am willing to share it.

My plan is as follows:

Run TAS5015 from external oscillator, maybe even 100MHz (though I have found swiss firm that produces 98.304Mhz oscillators http://www.microcrystal.com/Products...ku/MCSOHVT.pdf ) and use AD1895 or AD1896 asynchronous sample rate converter in front. All incoming data would be upsampled to 24 bit 192 khz and TAS5015 run in master mode.

Build discrete output stage with supply voltage up to 100V for the first design and maybe higher in next iteration. Output FETs would be Fairchild FDD3672 (44A, 28mE) which have very low gate charge, comparable to IRF520. Gate driver will be either HIP2100 from Intersil or discrete design using miniature pulse transformers (2.5mm ferrite toroids) with differential transformer between upper and lower gate driver to maintain proper dead time. I think this design would work pretty well, since I already tried it in analog class D amplifier.

I think it is better to optimize dead time (non overlap of conduction times of upper and lower FET in H-bridge) on driver and not to rely on PWM modulator. Anyhow, I think that there is actually no dead time between PWM_AP and PWM_AN outputs of any TAS50xx chip. Look at page 7 Figure1 of TAS5182 datasheet.

I also think it would be a good idea to physically separate modulator and output bridge section. I intend to use some Cat5 UTP cable and use LVDS chips to transmit and receive PWM information. If TAS5015 outputs are trully differential it would be even possible to use some resistive dividers on transmitting size.

I think separate approach has several merits: when new modulator comes along, it is necessary only to change modulator section, power section remains the same. I think also new developement will be in use of multiphase designs (look at Philips patent application "20020053945 Switching power amplifier"). It is relatively easy to add new phases with modular design. It may be even possible to use two TAS5015 modulators runing at 96kHz with skewed LRCLK. (just an idea, haven't look at it yet).

Advantage of multiphase design is: lower current in each halfbridge switching stage, lower switching frequency, ripple cancelation on output LC filter. I think also TI has found this since i suppose there is already some skew between left and right channel and also between A and B half of H-Bridge. (US patent 6373336 and US patent application "20020060605 Amplifiers").

Regarding power supply: I will use switching power supply with variable output voltage. Like in TACT design advantage is increased dynamic range and there is also less switching noise at low voltage and low volume.

Regarding dynamics of the power supply: switching power supplies can be made very fast. Look at the current multiphase designs for modern processors. So the best way would be to have isolated PFC conveter with large bank of capacitors on the secondary and relatively slow regulation loop (as PFC is supposed to do) and then multiphase synchronous buck converter. This would look almost exactly as already existing H-bridges and use same transistors and driver circuits.

Other possibility would be to use relatively simple power supply (mains transformer and rectifier with large capacitor bank) and use PEDEC (pulse edge delay error correction) by Niels Karsten.http://bogo-united.oeb.tdk.net/graph.../chapter_9.pdf. There is also similar technology to PEDEC http://pearlx.snu.ac.kr/Publication/PESC0203.pdf and maybe I can also think of something similar.

As I can see this project will take most of my free time next year.
Before I will make PCbs I would like to have some positive confirmation about timing of PWM outputs of TAS5015 chip. Is there actually no dead time between upper and lower PWM output and if there is actually time skew between left anf right channel and between left and right half of the each channel"s H-bridge? What would be best SPDIF receiver chip for the modulator and is there any advantage in using DF1704 oversampling filter?
Can anyone answer ?

Best regards,

Jaka Racman
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Old 21st December 2002, 12:17 PM   #52
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Digital filter is unlikely to be of much use as there is already some significant math going down in the TAS5015.

There is a companion chip which has been previewing on the TI site for a very long time which takes what I understand to be the balanced outputs (which have no skew) and sets up the rest of the bridge. I guess what I am trying to say is that there are two balanced signals controlling the entire bridge, and I believe this is what you asked to know. If you look at the lesser chips, they have single ended outputs performing the same function.

Petter
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Old 21st December 2002, 07:32 PM   #53
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Default Re: Re: Class BD

Quote:
Originally posted by Brian Brown
We're only beginning to see what I'm sure will be a flood of new switching amplifier techniques. While most efforts seem to be focusing on low cost, small size, and high efficiency, there's lots of stuff coming to raise the bar on sound quality. I'm very excited about the prospects.

I just hope that we, as individuals, get access to this new stuff.
Currently Hafler / Rockford holds the patent on the most recent class BD incarnation and i believe they sell them mostly in the pro-audio scene. The best part is there is no "all in one chip" for this type of technology. no DSP is required. they brought feedback back into the class D architecture and that took care of most everything as well or even better than DSP, without sacraficing stability.
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Old 21st December 2002, 08:03 PM   #54
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Quote:
Originally posted by Jaka Racman
I am new to this forum. I have just started drawing shematics for TAS5015 based amplifier. If the design will be any good I am willing to share it.
Hi!

I'm glad to hear you're working on this!

Quote:
My plan is as follows:

Run TAS5015 from external oscillator, maybe even 100MHz (though I have found swiss firm that produces 98.304Mhz oscillators http://www.microcrystal.com/Products...ku/MCSOHVT.pdf ) and use AD1895 or AD1896 asynchronous sample rate converter in front. All incoming data would be upsampled to 24 bit 192 khz and TAS5015 run in master mode.

Build discrete output stage with supply voltage up to 100V for the first design and maybe higher in next iteration. Output FETs would be Fairchild FDD3672 (44A, 28mE) which have very low gate charge, comparable to IRF520. Gate driver will be either HIP2100 from Intersil or discrete design using miniature pulse transformers (2.5mm ferrite toroids) with differential transformer between upper and lower gate driver to maintain proper dead time. I think this design would work pretty well, since I already tried it in analog class D amplifier.
BEAUTIFUL.

Quote:
I think it is better to optimize dead time (non overlap of conduction times of upper and lower FET in H-bridge) on driver and not to rely on PWM modulator. Anyhow, I think that there is actually no dead time between PWM_AP and PWM_AN outputs of any TAS50xx chip. Look at page 7 Figure1 of TAS5182 datasheet.
The PCM to PWM modulator chips (such as the TAS5012 and TAS5015) don't introduce any dead time to their PWM outputs.

The TAS5110 integrated H-bridge and the TAS5182 H-bridge driver chips DO introduce dead time. They do this by monitoring the gate charge of the output MOSFETs. This allows them to compensate for varying temperature and load characteristics. The dead time is adjusted by means of external resistors (Rdt - one for the high side of the bridge and one for the low side). In the case of the TAS5182, these are connected to pins 6 and 7, respectively.

From your initial description I'm presuming that you're planning to connect your output circuit directly to the TAS5015. In this situation you will need to implement your own dead-time control. (This probably is a better way to do it. I'm not going to be quite as ambitious in my first attempt, so I'm going to rely on TI's output chips.)

Quote:
I also think it would be a good idea to physically separate modulator and output bridge section. I intend to use some Cat5 UTP cable and use LVDS chips to transmit and receive PWM information. If TAS5015 outputs are trully differential it would be even possible to use some resistive dividers on transmitting size.
I can agree with you on the benefits of separating the output section, although this is another thing I won't be doing on my first attempt.

The TAS5015 outputs ARE NOT differential. They're single ended LVTTL referenced to ground. They have four separate lines for each transistor in the H-bridge because the timing between the uppers and lowers of the pairs is skewed.

Quote:
I think separate approach has several merits: when new modulator comes along, it is necessary only to change modulator section, power section remains the same. I think also new development will be in use of multiphase designs (look at Philips patent application "20020053945 Switching power amplifier"). It is relatively easy to add new phases with modular design. It may be even possible to use two TAS5015 modulators runing at 96kHz with skewed LRCLK. (just an idea, haven't look at it yet).
I'm not sure that the interface for a multiphase design would be compatible. At least it would be difficult before the data sheets of the new parts are released. I suppose it wouldn't hurt to take your best guess on what the requirements would be.

Quote:
Advantage of multiphase design is: lower current in each halfbridge switching stage, lower switching frequency, ripple cancelation on output LC filter. I think also TI has found this since i suppose there is already some skew between left and right channel and also between A and B half of H-Bridge. (US patent 6373336 and US patent application "20020060605 Amplifiers").
Thanks for listing these numbers!!!!

I had done a patent and application search when I first started this project and 20020060605 hadn't been published at the time.

I highly recommend that people who are interested in Equibit designs read this! It contains a detailed description of how Equibit works (although it doesn't use that name).

It turns out that I had a couple of misconceptions about how Equibit works. Particularly regarding the way it relies on sophisticated dither to eliminate quantizing errors that would otherwise happen when using a limited 384KHz carrier to modulated 24bit data.

Fortunately, my previous misunderstandings of the internals won't affect my circuit design.

Quote:
Regarding power supply: I will use switching power supply with variable output voltage. Like in TACT design advantage is increased dynamic range and there is also less switching noise at low voltage and low volume.

Regarding dynamics of the power supply: switching power supplies can be made very fast. Look at the current multiphase designs for modern processors. So the best way would be to have isolated PFC conveter with large bank of capacitors on the secondary and relatively slow regulation loop (as PFC is supposed to do) and then multiphase synchronous buck converter. This would look almost exactly as already existing H-bridges and use same transistors and driver circuits.
Nice. I like the idea of circuit re-use where possible.

Quote:
As I can see this project will take most of my free time next year.
Things always take longer than I expect.
Hopefully I'll have something working in a month or two.

Quote:
Before I will make PCbs I would like to have some positive confirmation about timing of PWM outputs of TAS5015 chip. Is there actually no dead time between upper and lower PWM output and if there is actually time skew between left anf right channel and between left and right half of the each channel"s H-bridge?
As I mentioned above, the TAS5015 doesn't introduce any dead time compensation.
There is a small amount of time skew in the carrier of the left and right channels to reduce crosstalk from the power supply. There's very large skewing differences between the halves of the H-bridge.

Quote:
What would be best SPDIF receiver chip for the modulator?
Since you're using the AD1896 ASRC, the choice of receiver chip is less critical.

I'm using a DIR1703, which allows the use of an external receiver (for better noise rejection). It's SpACT clock recovery algorithm is better than most because it isn't as data-dependant when looking at the incoming bi-phase mark stream. It is limited to 96KHz.

If you have a 192KHz source, the CS8416 would probably be a good choice. Besides the 192KHz compatibility, it has some nice features such as multiplexed inputs and automatic buffering of non-audio data. It's also probably a little bit easier to use. It's performance at 96KHz or lower isn't as good as the DIR1703, however.

Quote:
Is there any advantage in using DF1704 oversampling filter?
No.
The TAS5015 has its own built-in oversampling filter.

It's nice to have you along working on this!

Regards,
Brian.
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Old 22nd December 2002, 01:21 PM   #55
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Did anybody ever think of using a PCM1760 folllowed by a presettable counter to be used as a digital PWM generator (although with analog inputs) ? There would even be a few tricks possible to bring down the switching frequency and keeping the resolution the same, which could be implemented using some additional cheap standard logic ICs.

To R. McAnally:

I do not fully agree with you, regarding the stability issues for PWM amps.
If you take the feedback off before the output fillter, unconditional stability can be achieved much more easily than with ANY linear NFB amplifier type !!
If you want to include the output-filter, things start getting tricky though but still not unfeasible.
Do you know the patent # of the Hafler/Rockford amplifier ?
I wonder if their topology is really that new. I have done a lot of patent search on switching amplifiers and I must say that >95% of all the class-d patents are not covering really new ideas but are new variants of the circuit principle used within the famous Sony TA-88N amplifier (mine included ).
I know that TI has patents on class BD amps, where they use a multiphase bridge topology to achieve a BD - like behaviour. There are small IC amps available with this technology, intended to be used for small handheld devices where power consumption is of prime importance. These can be used without any output inductor and should still provide reasonable EMC figures (according to the manufacturer).
BTW: A real single-ended BD topology could be prone to crossover distortion.

Regards

Charles
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Old 23rd December 2002, 08:57 AM   #56
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Petter and Brian, thanks for the reply.

Since it seems there is interest how equibit works, I will list some of other patents:

Original patent, even before Toccata technology was formed: http://l2.espacenet.com/espacenet/bn...++9737433A1+I+

Enhancements to the switching stage (noise filtering and current sense):http://l2.espacenet.com/espacenet/bn...++9959241A2+I+ and http://l2.espacenet.com/espacenet/bn...++9959242A2+I+

Negative feedback from the output stage (seems it was never implemented):http://l2.espacenet.com/espacenet/bn...++0046919A2+I+ based on principle first conceived for analog class D:http://l2.espacenet.com/espacenet/bn...++9945641A1+I+

Regards,

Jaka
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Old 23rd December 2002, 09:25 AM   #57
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Hi Jaka

The first (and really novel) class-d patents are much older than these and they DID already include NFB !
The amp I built from discretes 10 years ago was based on an old Sony patent.

What I'd like zo know is the details about the BD amps mentioned by R. McAnally.

Regards

Charles
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Old 23rd December 2002, 04:49 PM   #58
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Default Re: Damping Factor

Quote:
Originally posted by Brian Brown
[B]In real life, an Equibit amplifier has no feedback at all to be screwed up by the back-EMF
Feedback is the reason traditional linear amps are so good at controlling back EMF. This is due to the extremely low output impedance (to the rails) it creates. True, too much back emf can cause instability, but this rarely EVER happens unless you are trying to drive a capacitor.

Quote:
Originally posted by Brian Brown
[B]<class D> it has a very direct low-impedance path between the power supply and speaker that is more effective at shunting out back-EMF.
it doesnt matter if the mosfet is half way on, or fully on half of the time. plain and simple, without feedback, you have a higher impedance to the rails, and in turn less cone control and DF. add to the fact the reactive nature of the output inductor(s) and you have even more impedance. adding a reactive load in this case only lessens the DF.

Quote:
Originally posted by Brian Brown
[B]So in terms of the 'Spirit of the meaning' of damping factor, an Equibit amplifier is superior to most others.

I'm surprised that TI included this spec in the report without any explanation.

simply because the output is switching is no excuse for poor damping =). this is why TI does not try to explain why 15 is a good damping ratio. it simply is not. your explaination holds no scientific water, and is simply wrong in some areas.

So where can i find this definition of "spirit of meaning"? it seems you have casually tried to define something with no real (or true) scientific backing. a subjective approach indeed.
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Old 23rd December 2002, 05:23 PM   #59
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Hi phase,


the patent number you are searching is US 6,097,249. Nothing special IMHO.

I have also built my first class D amplifier more than 10 years ago and it was based on now obsolete TDA7260 from SGS-Thomson.
(self oscillating with integrator and hysteresis comparator, like sigma delta but without clock and D-flip-flop.) It was actually used in PA system driving 8 horn loaded drivers in parallel (1ohm impedance).

Regards, Jaka
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Old 23rd December 2002, 06:02 PM   #60
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Hi Jaka

Thanks for the info. I already stumbled over this one a few weeks ago.
It is neither a sensation nor is it stupid. It does at least reduce RFI compared to a class AD amp.

Regards

Charles
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