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Old 17th December 2007, 08:46 AM   #521
Gyula is offline Gyula  Hungary
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Quote:
Originally posted by Eva
Open loop digital systems are a big no-no, a stupid dead-end

Power Supply Rejection Ratio is 0dB in these systems!!

On the other hand, closed loop digital systems are equivalent to any analog-controlled class D amplifier, but requiring fast, precise and expensive ADCs instead of standard DACs, so they are another dead end.
Hi Eva!

How could you define the 0 dB PSRR with a full-bridged amp.?
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Old 1st January 2008, 08:26 AM   #522
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Default PowerDAC3 development

Hi all

I have several photos of prototypes and pcb version of my new PowerDAC3 digital amplifier power module that when zipped result in a file of around 1.8MB.

I'd like to post these on the forum but the 100K attachment limit poses a problem. I've tried reducing the image size or jpg quality of these images so that each is less than 100K, but I feel the loss of detail is too great. As you know, with things like this the devil is in the detail.

Does anyone have any ideas on how to work around this in some way that does not compromise image quality?
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Old 1st January 2008, 09:05 AM   #523
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John, mail them to me and I'll have a look. I'll drop you a line so you have my email address.
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Old 1st January 2008, 11:30 AM   #524
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Default PowerDAC3 development

Here follow some photos of the PowerDAC3 prototype which I designed and built around 18 months ago, and first pcb version which I am presently testing.
Thanks to Al for compressing the pics for me without losing detail.

Proto1.jpg
Proto2.jpg
These show the single channel prototype OPS of the PowerDAC3 about halfway through development.

FDS3672phase2.jpg
This scope photo shows the 3.3V PWM logic drive signal and the OPS switching waveform on the OPS phase node at Vdc = 15V. Signal integrity is preserved over the full Vdc range of 1-60V.

Proto3a.jpg
Proto3c.jpg
Proto3d.jpg
These show the single channel OPS of the PowerDAC3 in the final prototype configuration completed around 18 months ago and which was taken to pcb. The OPS is an open-loop full bridge using SMD power devices and was tested to 350W into 4 ohms, 175W into 8 ohms. THD+N was around the 0.02% mark at all powers and efficiency was over 98%. The four discrete gate drivers are clearly visible in centre field, and the circuitry on the right hand side is output overload monitoring.

Pmod debugging.jpg
This shows the first pcb version of the PowerDAC3 Stereo Power Module which incorporates two of the OPS circuits from the protos, each of which has its own SMPS voltage regulator. The OPS feature an adaptive 'calibration algorithm' which is used to electronically optimise output stage switch timing and so eliminate the effects of ageing and parameter spread in MOSFet switching. The average current mode SMPS switch at the PWM switching frequency of 352,8kHz and are rated at 60V 10A continuous. They have an analog control loop with digital adaptive loop control, digital reference generation and supervision. PWM values are sent to the modulator in the form of signed 8-bit numbers from an external host, via a synchronous LVDS data interface. The Power Module incorporates a low-jitter reference clock synthesiser and a stereo PWM modulator. Regulator control, system monitoring, self-tests, and OPS calibration and is via a synchromous LVDS control interface.

The Power Module consists of two pcbs, namely an upper power board and a lower control board. These are normally mounted in a stack with standoff pillars between the two boards and interconnection via headers and header sockets. In the photo taken last December the two boards are separated during debugging and testing for access to components, and the interconnections are made with ribbon cable harnesses. Testing is still in progress. (Jan 2008)

All logic and control of the OPS and SMPS regulators, conversion of analog parameters for calibration, PWM generation and control is implemented in a single Actel Fusion FPGA which can clearly seen on the control board. Only the SMPS control loop core is implemented in analog.

This pic is proto1.jpg
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File Type: jpg pdac3-proto1.jpg (94.3 KB, 622 views)
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Old 1st January 2008, 11:31 AM   #525
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Default PowerDAC3

More pics. . .
Proto3a.jpg
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File Type: jpg pdac3-proto3a.jpg (95.9 KB, 593 views)
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Old 1st January 2008, 11:37 AM   #526
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Default PowerDAC3

More pics. . .
This is Proto3c.jpg
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File Type: jpg pdac3-proto3c.jpg (82.3 KB, 1016 views)
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Old 1st January 2008, 11:39 AM   #527
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Default PowerDAC3

More pics. . .
This is Proto3d.jpg
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File Type: jpg pdac3-proto3d.jpg (81.9 KB, 1081 views)
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Old 1st January 2008, 11:41 AM   #528
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Default PowerDAC3

More pics. . .
This is the scope shot FDS3672phase2.jpg
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Old 1st January 2008, 11:43 AM   #529
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Default PowerDAC3

More pics. . .

This is the first pcb version being debugged and tested
Pmod debugging.jpg

. . .nearly finished now. .
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File Type: jpg pmod-debugging.jpg (77.8 KB, 820 views)
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Old 1st January 2008, 11:45 AM   #530
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Default PowerDAC3

. . . and this is Proto2.jpg that somehow got lost in the sequence.

That's all, folks. I'll take more pics of the pcb version when I'm done testing it in a few weeks. Months? Hell, I dunno - most of it's working so far!

Cheers

John
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