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Class D Switching Power Amplifiers and Power D/A conversion

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Old 20th August 2007, 04:19 PM   #11
sovadk is offline sovadk  Denmark
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That is not bad for an open-loop design. I can imagine that he used large bank of supply decoupling capacitors or a smps to overcome the distortion caused by supply pumping. I remember having read that 0.01% THD in a open-loop full-bridge requires a supply impedance below 5mohm. For a hal-bridge design the impedance has to be even lower.
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Old 20th August 2007, 04:34 PM   #12
IVX is offline IVX  Russian Federation
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Yeah, they called it "Zero dead time switching", actually about 10nS into 20nS rise/fall edges. However Cirrus used ADC for tracking PSRR. You know, i can't find nothing about noise shaper in the tas5261.pdf..
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Old 21st August 2007, 01:40 PM   #13
sovadk is offline sovadk  Denmark
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It says in the TAS5261 datasheet "t(low) Minimum low-state pulse duration per PWM frame, noise shaper enabled 50 ns". In other words is has a build in noise shaper which is active as long as the pulse width is above 50ns.
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Old 21st August 2007, 05:05 PM   #14
IVX is offline IVX  Russian Federation
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Sovadk, ok, but THD performance of the TAS5261, rather the same, not better vs old chips at least. It's strange..
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