Mosfet driver IC's

[kartino]

Hi Tim,

Looked that you tried to speed up, the discharging of the mosfet's gates, by improving not just active clamps bipolar.

But according to my simulation, also Chris's seen that the discharging is already at that top speed.

I am fully agree with Lars, IMHO the only way is using JFET may be?

This is my last simulation. What I tried to do here is to share dissipation between Q6 and Q13 to get more current to drive the gates. Hence I can use smaller R6 and R8, also R8 and R11.

I also move the reverse bias for Q9 and Q11 directly to the collector of Q8 and Q10 to get fast off Q9, Q11. Also independence of gate charging.

By new arrangement, the control for dead time is the only by VR1 that in series with R1.

But it is still on simulation, but looked better than before.
Sadly I have no scope too.....!

[kartino]

This is in PDF,

BTW, is it not enough speed to do that job?

Actually I have did several ways seem as TiM did but i am unhappy with the result.

Best regards,
Kartino

[classd4sure]

Hello Mr. Kartino,

Are you sure this simulation works OK? Cuz I doubt it. I didn't have all the models you used so I had to make a few changes there, but I see definite error in the casdode circuit.

I made a few changes though and so far I can't believe how good it's working ......... something's got to be wrong?!?

Will post it after I beat it around some more..... sadly, it's also giving me some crazy new ideas.

[alfsch]

hi kartino,
i tried a gate driver - about same circuit - and it works fine, with low load :-)
so with irf530 at +-40v no problem.
but more votage, more problems...with irf640 at +-65 switching is too slow, fets loosing about 2w, gate seems like a 10nf cap !
to get it running at +-80v , driver has to be faster, but i have no idea , who to do it (without more components, driver ic, much more current drive ), because : driving a 5nf cap works fine, about 100ns switching, but not the irf640; whats so different (gate is like a cap, or )?

[av-trouvaille]

Hello,

A contribution with some lateral thinking.
- The recent thread by Kanwar/Workhorse on a driver stage might be interesting here. A quote from halfway this thread: ‘The Driver stage is actually a PUSH-PULL type..which ACTIVELY TURNS-OFF the FET, thus eliminating the Cross-Conduction and improves the Transient response at HF’ More at: NVMOS amplifier

- One other angle to enrich the reflexion process on driving mosfets is from the tubes world, where a grid choke apparently can help to drive an output tube more easily. This instead of the traditional grid resistor. I don’t know if/how this can be translated into solid state. Maybe someone else can?

My two cents, Arjen.

[classd4sure]

He's not using that as a switching amp, we're talking a whole new ballgame. Actually that whole design is heavily borrowed upon from a switching amp, the mosfet needs to be actively held off.

[kartino]

Hello Chris,

It is just on simulations, but IMHO what i've did make better than it was.

Hello Alf. I see you also working on the same "UcD". See my idea to share the dissipation for Q3 and Q11 at your schematic. Also IMHO R7, R9, R10, R12, use smaller value to get faster switching. Of course you need to set again the value for R6 and not to give much dissipation to Q11. (VCE almost -rail to +rail).

hi, do you think you have enough supply for your gates?

Regards,
kartino

[Workhorse]

Originally posted by classd4sure
He's not using that as a switching amp, we're talking a whole new ballgame. Actually that whole design is heavily borrowed upon from a switching amp, the mosfet needs to be actively held off.

Hi,

That amp is a Linear one not switching type, its driver configuration is based on exactly as in switching amps to improve the performance and utilize the mosfets in better way in Linear Domain...

K a n w a r

[kartino]

Hi Tim,

base on LTSpice file from you, looked that your overall speed at about 200kHz at rate, far from mine that 300kHz at rate. What's wrong with the simulation??

You also have problem for dissipation for Q13, for higher voltage,

waiting good news from you!

regards
kartino

[analogspiceman]

Here's my two cents worth on the discrete driver problem:

The high side driver always has a node that "sees" the entire voltage swing of the output stage added on top of the gate voltage swing.  Since i = c dv/dt, the current required to slew this node at the same speed as the equivalent node of the low side driver is greater by the ratio of the gate drive voltage swing to that of the output voltage swing (plus the gate drive voltage swing).  This is a manifestation of the so called "Miller" effect (it makes the high side node's capacitor appear to be much bigger than it really is).

The above is a best case scenario.  When there is a significant time delay through the driver signal chain, then the Miller effect may be delayed as well and show up either as a transition "oscillation" where the output bounces back and forth several times instead of making one clean jump, or as a "sticky" transition lockout that limits the minimum output pulse width.  Obviously, the former is very bad from both a noise and switching loss point of view, whereas the latter is usually very tolerable (often this effect, which is actually a form of positive feedback, speeds up the transition, lowering switching losses).

Which one of these you get depends on the polarity of the signal on the dv/dt sensitive node of the high side drive.  Relocating or adding in an extra inversion within the drive chain can change a bouncy drive type to a sticky drive type.

By the way, splitting the dv/dt voltage transition across two transistors seems like a very worthwhile idea as it should reduce the Miller effect to half of what it was before.

Regards -- analogspiceman