reducing UcD dead time distortion by Increasing Ripple Current
Hi All,
This is my first post, and I apoligize if this has been addressed already. I did search!
My understanding is that dead time is the root of most distortion in class D amps. The uncertainty in the switching time caused by the dead time and the polarity of the inductor current causes an error signal.
That is, when the inductor is sinking current, the transistion from SW node from high to low happens when the top switch current drops below the inductor current. i.e. when the top switch shuts off.
When the inductor is sourcing current, even when the top switch is off, the SW node stays high until the bottom switch is sinking the inductor current.
The differnence is roughly the dead time. I've measured this in real circuits, and I believe this is the beast to be tamed.
I've also noted that many class D amplifiers measure very low distortion when the output current delivered is less than half the ripple current.
I suspect there is terminology for this "class" of operation, but I don't know what to call it. Any buzz words to improve my search would be great!
I'd like to make a class D amp that had much higher ripple current.
Like a UcD700 that does 50~100 Watts of output with ~10A of ripple current. The "Class A" of "Class D" if you will.
I'd like to have a name for this type of operation for future discussions. Perhaps Bruno or someone else would have a term for this state of operation, or could coin one.
Thanks
Portland Mike
Hi All,
This is my first post, and I apoligize if this has been addressed already. I did search!
My understanding is that dead time is the root of most distortion in class D amps. The uncertainty in the switching time caused by the dead time and the polarity of the inductor current causes an error signal.
That is, when the inductor is sinking current, the transistion from SW node from high to low happens when the top switch current drops below the inductor current. i.e. when the top switch shuts off.
When the inductor is sourcing current, even when the top switch is off, the SW node stays high until the bottom switch is sinking the inductor current.
The differnence is roughly the dead time. I've measured this in real circuits, and I believe this is the beast to be tamed.
I've also noted that many class D amplifiers measure very low distortion when the output current delivered is less than half the ripple current.
I suspect there is terminology for this "class" of operation, but I don't know what to call it. Any buzz words to improve my search would be great!
I'd like to make a class D amp that had much higher ripple current.
Like a UcD700 that does 50~100 Watts of output with ~10A of ripple current. The "Class A" of "Class D" if you will.
I'd like to have a name for this type of operation for future discussions. Perhaps Bruno or someone else would have a term for this state of operation, or could coin one.
Thanks
Portland Mike
Hi,
your idea is actually quite old. It is no new class of amplifier. Appropriate search terms would be ZVS (zero voltage switching) and "resonant transition". Here is an old APT application note that deals with your idea.
Best regards,
Jaka Racman
your idea is actually quite old. It is no new class of amplifier. Appropriate search terms would be ZVS (zero voltage switching) and "resonant transition". Here is an old APT application note that deals with your idea.
Best regards,
Jaka Racman
I don't its ZVT exactly.
What I attempted to discribe is not really ZVT.
What I'm talking about is how when the load current in any class D amp is smaller than the half the ripple current in the inductor, the affective dead time is zero. i.e. The switch transition happens when the conducting switch shuts off. The switch node flies to to other rail becuase the inductor current is pulling there, and turns on the body diode of the still non-conducting switch.
During the dead time the body diode conducts, but is a relitively small error from ideal switching compared to the dead time induced error.
For example, if you have 40nS of dead time in ~500kHz Class D, you have an error pulse that is roughly 40nS/1uS *100%~4%
(This is very crude, but I think it gets the idea accross.)
That's 4% error for that switching half cycle!
This error pulse happens whenever the inductor current changes from:
All positive current though the whole cycle.
Alternating current through the whole cycle.
All negative current through the whole cycle.
These changes of coarse happen as load current is being delivered in amplitudes greater than 1/2 the ripple current.
I hope I'm beginning to clarify.
Its also a delay error t0o, and in UcD's I suspect this contributes to more frequency shift, and thus changes in the loop gain too.
Thanks
Portland Mike
What I attempted to discribe is not really ZVT.
What I'm talking about is how when the load current in any class D amp is smaller than the half the ripple current in the inductor, the affective dead time is zero. i.e. The switch transition happens when the conducting switch shuts off. The switch node flies to to other rail becuase the inductor current is pulling there, and turns on the body diode of the still non-conducting switch.
During the dead time the body diode conducts, but is a relitively small error from ideal switching compared to the dead time induced error.
For example, if you have 40nS of dead time in ~500kHz Class D, you have an error pulse that is roughly 40nS/1uS *100%~4%
(This is very crude, but I think it gets the idea accross.)
That's 4% error for that switching half cycle!
This error pulse happens whenever the inductor current changes from:
All positive current though the whole cycle.
Alternating current through the whole cycle.
All negative current through the whole cycle.
These changes of coarse happen as load current is being delivered in amplitudes greater than 1/2 the ripple current.
I hope I'm beginning to clarify.
Its also a delay error t0o, and in UcD's I suspect this contributes to more frequency shift, and thus changes in the loop gain too.
Thanks
Portland Mike
Hi,
I don´t quite follow you here. At the end, voltage waveform of the output stage gets integrated by the output filter. How you achieve fast transitions (by ZVS or by large cross conduction current) is really not important. It is the shape of the voltage waveform that is important.
Best regards,
Jaka Racman
I don´t quite follow you here. At the end, voltage waveform of the output stage gets integrated by the output filter. How you achieve fast transitions (by ZVS or by large cross conduction current) is really not important. It is the shape of the voltage waveform that is important.
Best regards,
Jaka Racman
Portlandmike
Your idea to increase ripplecurrent will generate more resistive losses in FETs and the inductor as well as more AC losses in the core. Another way of achieving the same improvement is basically to minimize the dead time all the way so that the difference, between when the output current is less than the ripple current and not, is very small. This will also generate more losses.
Keep in mind that globally modulated topologies depend a lot on the amplitude on the swiching residual. You may have to increase the filter cap if you decrease the inductor.
Your idea to increase ripplecurrent will generate more resistive losses in FETs and the inductor as well as more AC losses in the core. Another way of achieving the same improvement is basically to minimize the dead time all the way so that the difference, between when the output current is less than the ripple current and not, is very small. This will also generate more losses.
Keep in mind that globally modulated topologies depend a lot on the amplitude on the swiching residual. You may have to increase the filter cap if you decrease the inductor.
Pabo said:
Pabo,
I understand that it will be less effecient, but still very effecient.
I also think that Hypex for example has minimized dead time, but I haven't measured it. I suspect its still on the order of 20~30nS. Maybe this month I'll get to actually measuring it.
And yes, you need to increase the output C to keep the LC resonance the same, if that is the desire.
I have some 16uH 20A inductors waiting for a try, and I just ordered some "extra" UcD modules to play with.
Warm Regards,
Mike
Hi
You can also place a capasitor across the fets, in order to reduce distortion. The capasitor will clamp the inductor to either of the rails within the dead time period. This is exactly the same effect that a large rippel current has.
Off course this will increese the switching loss, but according to the following AES paper, good performance can be achieved without incresing the losses much.
AES 27th:
"Reducing of power stage THD by adding output capacitance" by Gaël Pillonnet, Nacer Abouchi and Philippe Marguery
I can mail this paper to you if you're interested.
You can also configure the output stage as a N+P-ch voltage follower and "eliminate" deadtime. The problem is designing the driver and making it fast enough.
Regards
Kaspar S. Meyer
You can also place a capasitor across the fets, in order to reduce distortion. The capasitor will clamp the inductor to either of the rails within the dead time period. This is exactly the same effect that a large rippel current has.
Off course this will increese the switching loss, but according to the following AES paper, good performance can be achieved without incresing the losses much.
AES 27th:
"Reducing of power stage THD by adding output capacitance" by Gaël Pillonnet, Nacer Abouchi and Philippe Marguery
I can mail this paper to you if you're interested.
You can also configure the output stage as a N+P-ch voltage follower and "eliminate" deadtime. The problem is designing the driver and making it fast enough.
Regards
Kaspar S. Meyer
sovadk said:
Sounds interesting, I'll email you for a copy, thanks.
I find it hard to believe you can put it on the switch node though.
I actually simulated a N+P follower output. The problems are the same old ones, just harder to manage since its basically one driver for both fets. A fet doesn't turn off just becuase its gate is turned off, it takes time for the charge to disipate.
Mike
Kaspar, I'd appreciate a copy of that paper emailed to me please.
It would increase switching loss by slowing the slew rate of the switching, secondary effects should be investigated as well... perhaps it would best be imiplemented as part of the usual snubber networks.
Then again I do think ZVS has the best merits here.
As Mike states energies do take time to dissipate, but in ZVS those energies are greatly reduced, enough to allow switching frequencies into the low MHz range, with a reduction of EMI, all things ideal.
It would increase switching loss by slowing the slew rate of the switching, secondary effects should be investigated as well... perhaps it would best be imiplemented as part of the usual snubber networks.
Then again I do think ZVS has the best merits here.
As Mike states energies do take time to dissipate, but in ZVS those energies are greatly reduced, enough to allow switching frequencies into the low MHz range, with a reduction of EMI, all things ideal.
classd4sure said:
Maybe I'm dim, but I don't see how to apply ZVS to a buck regulator, which is basically what a Class D is.
The original proposal to increase ripple current just fixes the delay to how long it takes to turn a switch from hard on, to less than the inductor current.
I'm interested in this paper, but I can't imagine enough capacitance on the switch node would help. If your inductor is doing amps.... it might slow the slew rate a bit, but I don't see how it changes the error pulse energy.
Adding more output cap does filter the error pulse though, and I suspect it might be another way of stating my original idea.
Mike
classd4sure said:
Well althouth the switching time didn't take longer, it would still increese the losses. Reson is, you have to charge and discharge the added capasitor f times per second. The loss becomes P_Cswitching=f*C*Uvcc^2
As you might think, this technique is not very suited for an amplifier with high voltage rails. At least if it requires a large capasitor.
I can't email you guys, but I've just enabled my own email option.
It turns out that you can't reduce distortion by increasing the ripple current. The effective threshold of mosfets is dependent on the current. This will cause nonlinear distortion. See:
http://www.diyaudio.com/forums/showthread.php?s=&threadid=76085
http://www.diyaudio.com/forums/showthread.php?s=&threadid=76085
Just remove dead time and slow down the dV/dT like Crest do in their LT amplifier....Or think about how to delay feedback to correct dead time distortion (a cue here...) and get better effiency!
Fredos
www.d-amp.com
Fredos
www.d-amp.com
Portlandmike!
Your idea theoretically works, and for example Lars Claussen almost realised it. In his amps (or just in the old ones?) inductor ripple current is very high, 4-5 Ap, so at moderate power there is no dead time distortion. But full power realisation (especially in UcD) involves some problem. Stress on decoupling capacitor, increasing EMI, etc...
I think UcD is already a very good amp, it doesn't really need this modification. Just set a minimal dead time!
sovadk!
From the other topic:
You are right, not all of the THD can be eliminated, but the nastiest part of it. Dead time induced nonlinearity generates high order harmonics, at low volume. If we make soft switching, then the residual timing problem is only the change in tdoff, wich is 1.: typically smaller then dead time, 2.: maximum 2nd order function of drain current, so only low order harmonics generated, 3.: it is almost constant at low output power, wich is the most important area in audio.
Of course there are other reasons of nonlinearity, but I think they don't have a knee in low power region.
Your idea theoretically works, and for example Lars Claussen almost realised it. In his amps (or just in the old ones?) inductor ripple current is very high, 4-5 Ap, so at moderate power there is no dead time distortion. But full power realisation (especially in UcD) involves some problem. Stress on decoupling capacitor, increasing EMI, etc...
I think UcD is already a very good amp, it doesn't really need this modification. Just set a minimal dead time!
Neither do I.
sovadk!
From the other topic:
You are right, not all of the THD can be eliminated, but the nastiest part of it. Dead time induced nonlinearity generates high order harmonics, at low volume. If we make soft switching, then the residual timing problem is only the change in tdoff, wich is 1.: typically smaller then dead time, 2.: maximum 2nd order function of drain current, so only low order harmonics generated, 3.: it is almost constant at low output power, wich is the most important area in audio.
Of course there are other reasons of nonlinearity, but I think they don't have a knee in low power region.
If you have a large Ron on your MOSFETs, then they would start tozilog said:
conduct when the output swing of the amplifier is large. This can
easily give more than 1% of open-loop distortion.
Have a look at these following graphs. They're made with the MATLAB
script THDcalc by Flemmeing Nyboe:
http://www.diyaudio.com/forums/showthread.php?s=&threadid=76085&perpage=10&pagenumber=3
There's also a paper on how he models what happens within the
deadtime period.
THD versus Ron
With a large Ron the bodydiode will start conducting at large
output swings. This has nothing to do with what happens within the
deadtime periode, but it will cause distortion. This effect
dominates at high power levels.
An externally hosted image should be here but it was not working when we last tested it.
THD versus the output capacitance of the output stage.
A high output capacitance clamps the voltage within the deadtime
period an effectively lowers distortion. This does unfortunaly
increase the power dissipation in the power stage.
An externally hosted image should be here but it was not working when we last tested it.
THD versus ripple current
Yes, as you say, it can be eleminated at low power levels. Have a look here.Pafi said:
A large ripple current can decrease the distortion a low power
levels, but it has no effect at large power levels. I think that a
ripple current above 1A is mandatory, but going much higher should
be done with care.
An externally hosted image should be here but it was not working when we last tested it.
THD versus desdtime
Last but not least, what all of you already knew something about.
An externally hosted image should be here but it was not working when we last tested it.
I think that these graphs shows that THD depends on many
parameters. If you have a large power stage output capacitance,
low Ron and a high ripple current, then the effect of deadtime can
be minimized.
So if you buy the newest MOSFETs with a low output capacitance,
you'll get a higher THD than with your old MOSFETs (with a large
capacitance and Ron). On the other hand your old design might
sound bad at large power levels because the Ron is too high.
Everything has to be taken into account and this is what makes switching amplifier design so much more challenging than power supply design. I think that this shows that you need to simulate things a lot before building them. It's very difficult to make a good sounding amplifier if you haven't been working in front of you computer with open-loop distortion, feedback and small signal modelling , before you start building things. Most of the tools are all there, however ther's still at lot of things to research.
Btw. some of you requested this:
fredos said:
Adding the extra two inductors between output FETS in exchange for no deadtime does not solve the deadtime problem. Using the extra two inductors along with zero dead time just reduces the peak common mode conduction current between the two FETS during switching transitions. As a result of voltage second imbalance the quiescent current will rise dramatically in the FETS and inductors if there is no way of dissipating this energy or returning it back to the supply. The current will increase in the FETS and inductors until equilibirum is obtained when the increase in energy per cycle in the inductors equals the energy loss per cycle in the drain-source resistance of the FETS. This could result in a large current (several amps) being drawn from the supply instead of milliamps. So the addition of the two inductors still needs some dead time.
Crest use an RC snubber across the FETS which forms a lossy tank circuit which is probably used to dissipate the excess inductor energy similar to a resonant switch mode supply but this seems like a bit of a fiddle to get exactly right. In any event the effects of zero dead time and common mode conduction will still be be an issue with this type of circuit.
Yes it could, but it won't if you do it well. Times can be set with 5 ns precision. 5 ns at 400 kHz and Vdd=150V means 0,3V. 0,3V at (drain resistance of MOSFET + differential resistance of diode + Rdc of inductor)=0,1 ohm (typical) is 3A. This is 0,9 W conduction loss (per buck converter). Plus a lot more switching loss. But if you achieve fast switching transients, it can be moderate. Eg. 150V*3A*50ns/2,5us=9W.
Edit: I forgot diode loss: 0,8V*3A/2=1,2W. (Per buck converter.)
I've just finished one. Without any dead time adjustment I had a relatively high idle current (5A), and 300 mA supply current in a 40A 180V full bridge. Then I increased gate discharge current, so idle current is 3A now, and supply current dropped to 180 mA.
- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.