reducing UcD dead time distortion by Increasing Ripple Current

[Portlandmike]

reducing UcD dead time distortion by Increasing Ripple Current

Hi All,

This is my first post, and I apoligize if this has been addressed already. I did search!

My understanding is that dead time is the root of most distortion in class D amps. The uncertainty in the switching time caused by the dead time and the polarity of the inductor current causes an error signal.
That is, when the inductor is sinking current, the transistion from SW node from high to low happens when the top switch current drops below the inductor current. i.e. when the top switch shuts off.
When the inductor is sourcing current, even when the top switch is off, the SW node stays high until the bottom switch is sinking the inductor current.
The differnence is roughly the dead time. I've measured this in real circuits, and I believe this is the beast to be tamed.

I've also noted that many class D amplifiers measure very low distortion when the output current delivered is less than half the ripple current.

I suspect there is terminology for this "class" of operation, but I don't know what to call it. Any buzz words to improve my search would be great!

I'd like to make a class D amp that had much higher ripple current.
Like a UcD700 that does 50~100 Watts of output with ~10A of ripple current. The "Class A" of "Class D" if you will.

I'd like to have a name for this type of operation for future discussions. Perhaps Bruno or someone else would have a term for this state of operation, or could coin one.

Thanks

Portland Mike

[Jaka Racman]

Hi,

your idea is actually quite old. It is no new class of amplifier. Appropriate search terms would be ZVS (zero voltage switching) and "resonant transition". Here is an old APT application note that deals with your idea.

Best regards,

Jaka Racman

[Portlandmike]

What I attempted to discribe is not really ZVT.

What I'm talking about is how when the load current in any class D amp is smaller than the half the ripple current in the inductor, the affective dead time is zero. i.e. The switch transition happens when the conducting switch shuts off. The switch node flies to to other rail becuase the inductor current is pulling there, and turns on the body diode of the still non-conducting switch.

During the dead time the body diode conducts, but is a relitively small error from ideal switching compared to the dead time induced error.

For example, if you have 40nS of dead time in ~500kHz Class D, you have an error pulse that is roughly 40nS/1uS *100%~4%
(This is very crude, but I think it gets the idea accross.)
That's 4% error for that switching half cycle!

This error pulse happens whenever the inductor current changes from:
All positive current though the whole cycle.
Alternating current through the whole cycle.
All negative current through the whole cycle.

These changes of coarse happen as load current is being delivered in amplitudes greater than 1/2 the ripple current.

I hope I'm beginning to clarify.

Its also a delay error t0o, and in UcD's I suspect this contributes to more frequency shift, and thus changes in the loop gain too.


Thanks

Portland Mike

[Jaka Racman]

Hi,

I don´t quite follow you here. At the end, voltage waveform of the output stage gets integrated by the output filter. How you achieve fast transitions (by ZVS or by large cross conduction current) is really not important. It is the shape of the voltage waveform that is important.

Best regards,

Jaka Racman

[Pabo]

Portlandmike

Your idea to increase ripplecurrent will generate more resistive losses in FETs and the inductor as well as more AC losses in the core. Another way of achieving the same improvement is basically to minimize the dead time all the way so that the difference, between when the output current is less than the ripple current and not, is very small. This will also generate more losses.

Keep in mind that globally modulated topologies depend a lot on the amplitude on the swiching residual. You may have to increase the filter cap if you decrease the inductor.

[Portlandmike]

Originally posted by Pabo
Portlandmike

Your idea to increase ripplecurrent will generate more resistive losses in FETs and the inductor as well as more AC losses in the core. Another way of achieving the same improvement is basically to minimize the dead time all the way so that the difference, between when the output current is less than the ripple current and not, is very small. This will also generate more losses.

Keep in mind that globally modulated topologies depend a lot on the amplitude on the swiching residual. You may have to increase the filter cap if you decrease the inductor.

Pabo,

I understand that it will be less effecient, but still very effecient.
I also think that Hypex for example has minimized dead time, but I haven't measured it. I suspect its still on the order of 20~30nS. Maybe this month I'll get to actually measuring it.

And yes, you need to increase the output C to keep the LC resonance the same, if that is the desire.
I have some 16uH 20A inductors waiting for a try, and I just ordered some "extra" UcD modules to play with.

Warm Regards,

Mike

[sovadk]

Hi

You can also place a capasitor across the fets, in order to reduce distortion. The capasitor will clamp the inductor to either of the rails within the dead time period. This is exactly the same effect that a large rippel current has.
Off course this will increese the switching loss, but according to the following AES paper, good performance can be achieved without incresing the losses much.

AES 27th:
"Reducing of power stage THD by adding output capacitance" by Gaël Pillonnet, Nacer Abouchi and Philippe Marguery

I can mail this paper to you if you're interested.

You can also configure the output stage as a N+P-ch voltage follower and "eliminate" deadtime. The problem is designing the driver and making it fast enough.

Regards
Kaspar S. Meyer

[Portlandmike]

Originally posted by sovadk
Hi

You can also place a capasitor across the fets, in order to reduce distortion. The capasitor will clamp the inductor to either of the rails within the dead time period. This is exactly the same effect that a large rippel current has.
Off course this will increese the switching loss, but according to the following AES paper, good performance can be achieved without incresing the losses much.

AES 27th:
"Reducing of power stage THD by adding output capacitance" by Gaël Pillonnet, Nacer Abouchi and Philippe Marguery

I can mail this paper to you if you're interested.

You can also configure the output stage as a N+P-ch voltage follower and "eliminate" deadtime. The problem is designing the driver and making it fast enough.

Regards
Kaspar S. Meyer

Sounds interesting, I'll email you for a copy, thanks.

I find it hard to believe you can put it on the switch node though.

I actually simulated a N+P follower output. The problems are the same old ones, just harder to manage since its basically one driver for both fets. A fet doesn't turn off just becuase its gate is turned off, it takes time for the charge to disipate.

Mike

[Portlandmike]

Originally posted by sovadk
AES 27th:
"Reducing of power stage THD by adding output capacitance" by Gaël Pillonnet, Nacer Abouchi and Philippe Marguery

I can mail this paper to you if you're interested.
Regards
Kaspar S. Meyer

Kaspar,

I tried to email you but it wouldn't allow it.
Can you email me, then I'll respond?

Thanks

Mike

[classd4sure]

Kaspar, I'd appreciate a copy of that paper emailed to me please.

It would increase switching loss by slowing the slew rate of the switching, secondary effects should be investigated as well... perhaps it would best be imiplemented as part of the usual snubber networks.

Then again I do think ZVS has the best merits here.

As Mike states energies do take time to dissipate, but in ZVS those energies are greatly reduced, enough to allow switching frequencies into the low MHz range, with a reduction of EMI, all things ideal.