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Old 20th December 2005, 02:57 PM   #1
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Default dv/dt turn on with ir2011 simulation

I found a subcircuit & model for the ir2011 for ltspice here (had a nice subcircuit with it too, think it was posted up here by analogspiceman, correct me if you never posted any such thing!) anyway i'm simulating a simple half bridge with oodles of dead time in LTspice & had to alter tolerance parameters (to make the simulation run stably) as outlined in a text file with the model.
I'm getting significant dvdt turn on problems, namely when the opposite fet is switching the gate drive of the other spikes momentarily causing a significant shootthru.
I've tried slow down resistors & schottkys on the gates but still have similar problems. Now maybe it's a poor choice of fets (modelled with irf540/640/840 only) perhaps choosing a more suitable fet would alieviate the problem? Or could i be bogged down with simulation woes? Maybe linear tech have some cunning code to detect when ltspice is simulating competitors products & produce bad results
I'd post the circuit & models up except i'm not simulating on my posting machine (its too slow!)
Also any general tips & advice on simulating gate driver IC's would be useful... Ideally i'd like my real version of the circuit to behave almost as well as the final simulated prototype

cheers
Rob
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Old 20th December 2005, 03:06 PM   #2
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What's the dimensioning of your gate series resistors ? Are the diodes connected the right way around ?

Regards

Charles
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Old 20th December 2005, 03:07 PM   #3
poobah is offline poobah  United States
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Oldroborg, what is the level of the gate spikes you are seeing?

And are you seeing a bonafide shoot-thru current? The gate to drain capacitance of the idle FET will always be there... so there will also be a charge current.

Got schem?
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Old 20th December 2005, 03:17 PM   #4
SSassen is offline SSassen  Netherlands
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If you're referring to my class-D amplifier thread I can tell you that analog spiceman's model does noet need tampering, it runs fine as is, something in your circuit is causing it to act up.

Best regards,

Sander Sassen
http://www.hardwareanalysis.com
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Old 20th December 2005, 06:32 PM   #5
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@phase_accurate: i tried everything from no gate resistor to over 20ohms, same gate drive spike & both fets on for a brief moment.
@poobah: Fairly small, few volts, although i tried many configurations so had a great variation of effects. They look like short shoot thrus as the simulations start OK with a fet current of less than 10 amps or so, then a while into the simulation it gets spikes of over 40amps, maybe it is a capacitance, as it's a very short current spike.
@ssassen: the model worked in LTspice without any problems with one 2011 but then i tried two to produce a full bridge & i had to increase reltol & abstol by a factor of ten to get ltspice to to stop bailing out or produce currents of gigaamps and teravolts from a 100v supply Would be good for a solid state tesla coil, but not so handy for an 8ohm loudspeaker!

i'll bring the schematic in tomorrow, need to buy some cdrs first
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Old 20th December 2005, 07:39 PM   #6
SSassen is offline SSassen  Netherlands
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Oldoborg,

I've done several full bridge designs, up to 2KW in 4-ohms to be exact, in LTspice and never had that problem. Do keep a close eye on the MOSFET gate resistors though, they need to be in the 33~82-ohm range, not 10-ohm as per the IR datasheet, that will result in monstercurrents and Terawatts of power drawn due to cross-conduction.

If you like fwd me your LTspice .asc file and I'd be happy to take a look, feel free to email me at ssassen(at)hardwareanalysis(dot)com. I can't promise anything of course, but I'm sure you're missing something somewhere that breaks the simulation somehow.

Best regards,

Sander Sassen
http://www.hardwareanalysis.com
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