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Class D Switching Power Amplifiers and Power D/A conversion 

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18th December 2005, 10:01 PM  #1 
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Is the UcD modulation scheme less than optimum?
There is a recent paper out of the Technical University of Denmark by Poulsen and Andersen that compares the classd audio performance of various types of selfoscillating power convertor topologies: Self Oscillating PWM Modulators, a Topological Comparision
They claim that the phase shift sinewave feedback of the UcD type modulator circuit is measurably worse than the sawtooth feedback of an optimized hysteresis design. This, they claim, is because the straight lines of a sawtooth lead to more linear large signal modulation and transient behavior when compared to the curvy lines of the UcD type modulator (especially when operating at high levels near the peaks of the sine wave feedback signal). They call their intentionally linearized hysteresis circuit, AIM (astable integrating modulator), and call the phaseshift, selfoscillation modulation scheme utilized by the UcD family, COM (controlled oscillation modulator). Their implementation of their AIM circuit also largely eliminates the problematically large frequency excursions suffered by standard hysteresis modulators. Like many such papers, this one and the others in this series, aren't especially good at clarifying design details or explaining how it all really works (probably this is intentional). They include some schematics, but they are reduced in size to the point that the component values are illegible. After a just a few readings, I have only a tentative opinion as to what they are up to (and reserve the right to completely reverse myself ), but it seems that there are two pillars upon which rests the foundation of their design. First, they take into account the contributions at the switching frequency of all of the feedback paths to the modulator, including any little bits of carrier that get through via global feedback. These are all summed and shaped over frequency to achieve a first order ideal integrator at the modulator input, which is what is necessary to produce the ideal linear sawtooth from the rectangular output stage switching waveform. Second (and this is the novel part I'm less sure of), they cascade two hysteretic comparitors in series, the first of which is the usual one, and the second of which seems to provide a moreorless fixed time delay that generates a significant portion of the phase shift that determines the frequency of self oscillation (although they don't describe it in these terms). As to the answer to the question of the subject line, I haven't made up my mind, yet. Time permitting, I intend to draw up and post simulation schematics of this idea to compare against the UcD and others. By the way, I have access to these papers through the IEEE and my local university library, but, so far, I haven't found any freely available online copies (those seriously interested and who promise to share their studied opinions of the paper on this forum may contact me by email). Regards  analogspiceman 
18th December 2005, 11:08 PM  #2 
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Hi,
I already have one paper by the same guys "Hysteresis Controller with constant switching frequency". I'd like to see this one as well. Feel free to email it to me. Regards, Chris 
18th December 2005, 11:19 PM  #3  
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Quote:
Thanks, Chris 

19th December 2005, 12:00 AM  #4 
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The usual selfpromoting academic papers.
AIM or COM or UcD can't have constant switching frequency due to finite amount of time the error signal stays on one side of the average when the modulation index approaches 1, therefore in order to keep the duty ratio proportional to the reference (audio) signal, the period has to become longer. BTW Dr. Poulsen now works for IcePower.
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19th December 2005, 12:18 AM  #5  
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Quote:
I think they sponsored his thesis too if I'm not mistaken, so those papers promote a little more than just the self involved. The paper I mentioned is a different beast than AIM however. It doesn't seem to be available anymore either. 

19th December 2005, 12:19 AM  #6 
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Ideal modulator?
I don't buy Poulsen's and Putzeys's argument that the sawtoothlike modulating signal should be as close to a sawtooth as possible. My reason is that the slope of the modulating signal is inversely proportional to the open loop gain. Therefore at high modulation index if the slope at the top end of the modulating signal decrease due to lowpass filter effects, the loop gain would be higher therefore THD would benefit from such higher loop gain.
Comments welcome
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19th December 2005, 02:48 AM  #7 
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May be possible, I have thought of it before. But anyone has a real measurement / simulation / calculation?
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Ideal OP doesn't make perfact linars but make perfact switchers. 
19th December 2005, 07:31 AM  #8  
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Hysteresis Controller with Constant Switching Frequency Søren Poulsen and Michael A. E. Andersen, Member, IEEE IEEE Transactions on Consumer Electronics, Vol. 51, No. 2, MAY 2005 it is still available from the IEEE. It is the one with the unreadable schematics that I mentioned earlier. There is another paper by Poulsen and Andersen that may be of interest: Simple PWM Modulator Topology with Excellent Dynamic Behavior, IEEE APEC, Feb 2004 Abstract: "This paper proposes a new PWM modulator topology. The modulator is used in switch mode audio power amplifiers, but the topology can be used in a wide range of applications. Due to excellent transient behavior, the modulator is very suited for VRMs or other types of DCDC or DCAC applications." The new modulator is a variation of AIM: "The modulator topology proposed in this paper, GLIM – GLobal Integrating Modulator, has the same basic characteristics as the AIM modulator, but operates with feedback signals taken from both the output of the power stage and the output filter. This gives benefits in form of suppression of errors due to power stage and output filter unlinearities, as well as increasing open load stability and closed loop bandwidth, with or without additional voltage feedback loops." In this and some of their other papers, they are implicitly using a combination of positive and negative feedback, but they don't seem to make any mention of it, so I'm not sure they are totally aware of it. Some of it is almost leapfroglike. They give a simplified schematic of a power supply example using GLIM circuitry. It was readable enough (just barely) to draw up an LTspice schematic. My simulation agreed exactly with their published results, although I'm not real certain that their circuit offers new advantages. Regards  analogspiceman PS: Did the paper come through okay? 

19th December 2005, 07:53 AM  #9 
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Hi,
IIRC, adding fixed delay after hysteretic modulator has already been patented. I think it was by Italian branch of the STmicroelectronics, but I am unable to find the patent again. IIRC, delay increases the open loop gain, and explanation of the patent was by graphical means. I would be interested in reading the paper, too. Best regads, Jaka Racman Edit: I have found the patent. It`s US 6343852 , but it is synchronised, not free running. 
19th December 2005, 09:19 AM  #10 
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The common view on modulation is that the voltage to duty cycle transfer ratio equals 1/ the probability density function of the carrier (whereby "carrier" means the intentionally added carrier if present plus all HF fed back through the whole feedback chain).
This is correct only when the carrier is constant and independent of the signal. That is patently not the case in amplifiers employing feedback, because a square wave with a varying duty cycle must necessarily have a varying HF content (it IS the HF content). In selfoscillating amps, the varying switching frequency becomes a further factor. To use of PDF of the HF at the comparator input in idle state in an attempt to predict modulator linearity with signal applied is quite useless, unless your amp has no feedback at all. Local gain of the modulation is more efficiently determined by the instantaneous frequency and dv/dt of the waveform at the comparator input, not what it looks like outside the zero crossings. It can be curved, straight, or even spikey if you will, the only thing that matters is that tiny stretch that crosses zero. That's what sets the gain at this very specific instantaneous modulation index. If you want to figure out if a given modulation scheme is linear, you have to run through this test or calculation for the entire modulation range. If the output filter is in the loop, the load impedance also becomes a factor in this. At a certain load impedance (guess which value), the UcD modulator is astoundingly linear up to nearly full signal swing. At higher and lower impedances, odd order effects show up, with positive sign for lower impedances and negative sign for higher impedances. You can't do much more optimum than to minimize the effect near rated impedance. Every amplifier that puts the output filter in the loop has this problem, quite regardless of whether they use a fixed carrier or not. Trying to find a simple trick to alleviate the effects of "ripple aliasing" (for lack of a better term) in amplifiers employing feedback around the output filter is a local hobby in Rotselaar, as much as it is in Copenhagen. In modulators employing substantial feedback before the output filter, solutions have been found independently by several people. I'm presenting a simple one the coming AES. In a bid to confuse the crowd I'm going to place it in the context of digital modulators . But it's fairly adaptable to analogue, don't worry. Anyhow, the upshot of the above is that for the time being, any amplifier intending to use only postfilter feedback, will have to make do with optimizing linearity at rated load. Anyone suggesting this is far from optimum should present a method free from this problem. 
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