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Old 14th July 2005, 12:08 AM   #31
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Ivan how come you can't read the gate waveform ?

Preferably, do what you have to do so you can read the gate waveform...

What I did was simply used temperature and sound cleanliness, that amp now has over 100 hours on it, easily.

Using older mosfets can be a huge help in preliminary testing, they slow things down imposing a soft dead time and also limits EMI, which you notice if it's a problem or not real fast. IRF640 has proven to be a true workhorse for these stages of testing, and take an unbelievable amount of abuse, more than enough to get you into the ballpark for testing with more optimal mosfets.

At which point I'd strongly suggest limiting gate driver voltage so that Vgs only see's enough to fully enhance it and no more, this is also to help limite EMI and the possibility of ringing.

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Old 14th July 2005, 06:23 AM   #32
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Chris,
i talk about chip solutions, where gates isn't accessible. I've tried resistive load totem pole, but can't see the dead time exactly. This is switching wave form (10ns/div) for the TDA8939, which claimed zero dead time, because rise/fall edges 20ns>10ns as dead time. So i want to check others accessible chips, just by looking to the totem pole switching. How?
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Old 14th July 2005, 06:34 AM   #33
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Hi Ivan,

Consider the following. Dead time manifests itself in various ways in the actual behaviour of the power stage. You might try to list a few of the most important ones and see if any of them are measurable, either on a fully operational amp or on a test circuit.

For example, on amplifiers with a clear "dead time hump" in the THD vs power response, extrapolation of the right hand slope of the hump to the clipping point allows you to calculate dead time with good accuracy (if you know the loop gain of course - open loop amps are easier in this respect). Dead time on the TDA8939 is too short for this though, but there are other even more direct metrics.
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Old 14th July 2005, 09:32 AM   #34
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Nice input, Bruno. But for such wise DT measurement, i need already well designed PCB for each chip, it so hard for me.. more direct -more attractive. This is switching screenshot for loaded(~15ns)/unloaded(~20ns) same chip (20uHn/1uF/8Ohm), it seems that DT is really zero :-) Well, I'll try to compare the rise vs fall edges for DC at the output..(pumping- scary movie).
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Old 14th July 2005, 10:05 AM   #35
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Quote:
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Nice input, Bruno. But for such wise DT measurement, i need already well designed PCB for each chip, it so hard for me.. more direct -more attractive. This is switching screenshot for loaded(~15ns)/unloaded(~20ns) same chip (20uHn/1uF/8Ohm), it seems that DT is really zero :-) Well, I'll try to compare the rise vs fall edges for DC at the output..(pumping- scary movie).
Considering that the switching behaviour of the chip will depend to some extent on the PCB layout, trying to determine "dead time" on a chip without a good PCB does not produce reliable readings.
Your scope plot shows differences in rise time, but not where the edge is with respect to the actual dead time... Triggering on the switching waveform itself is not informative.
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Old 14th July 2005, 07:38 PM   #36
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Such kind of PCB.. yeah, it's not given to me easily.
Actually, some assymmetry is well seen when "playing" DC. Just by fast looking (visual integration) the assymmetry maybe equivalent 5ns or less. I suspect, that also can try to read the driver supply current (boot strap pin), at least, in the simulation this current do things visible, however it is driver design depended.
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Old 14th July 2005, 07:41 PM   #37
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Ivan,

I was thinking of checking the ripple on the stab pins as well, but didn't think it would really tell the story.

Alternatively if you really wanna find out peel the top off the IC and take a thermograph to find the mosfets then you can probe it at the gate But how bad do you really wanna know? Can't ajust it anyway.
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Old 14th July 2005, 09:52 PM   #38
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Alternatively if you really wanna find out peel the top off the IC and take a thermograph to find the mosfets then you can probe it at the gate But how bad do you really wanna know? Can't ajust it anyway.
You can see where the mosfets are even with your bare eyes. No need to pull out a thermograph. These don't have a very high resolution.

I remember once, with an early version of the TDA8920, we were trying to get Ph Semicon to make smaller gate drive buffers (the EMI of the first chips was horrendous). So they made a set of test chips with various gate fet sizes to see which was best. Well, one chip was marked as having small drive fets but it radiated abnormally. Unfortunately the IC blew so that was the end of the test. I then decided to strip the IC. That is, I clamped it in a vise and knocked the top half off the package using a hammer and a chisel. The chip was reduced to bits, but the epoxy still carried the chip's imprint on it. The imprint was good enough to show, under moderate magnification, that the gate drivers were indeed large.

So, if you do manage to get at the die, knowing where to probe is not a big problem. Knowing how is another matter, because the IC is glass passivated. You'd need to etch a hole through this layer before you can measure anything.
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Old 15th July 2005, 09:45 AM   #39
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Chris, thanks,
your suggestion about a thermograph is really extraordinary.
BTW, i still can't find any offers for PWM controller before TDA8939 (here available ~5euro) at the www.philips.semicondcutors.com.
>1 year after press release..
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Old 21st July 2005, 07:23 AM   #40
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Default MOSfet switching explained

International Rectifier's Application Note 947 is a comprehensive article on MOSfet switching and worth wading through if you really want to understand the true grit of this matter. It's a bit of a mathematical horror, and is best studied over a period of a few days. With the aid of a glass of good red wine. In silence.

http://www.irf.com/technical-info/appnotes/an-947.pdf
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