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Old 29th June 2005, 11:57 PM   #21
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Quote:
Originally posted by Bruno Putzeys

...Hmmmm... I've often dreamt about making an adaptive control circuit that made for negative dead time so it always crosses over precisely at Id=Iout. Hugely interesting, both in terms of distortion and efficiency, but "fairly" impractical.

<snip>

This is quite obvious. As long as the FET is transitioning (Vds is moving down), the miller effect will insure that Vgs cannot move beyond the point corresponding with drain current.
It's quite simple, isn't it? If Vds>>0, Id is determined only by Vgs. If Vgs were higher, either Vds should be 0 or there should be shoot-through preventing Vds from coming down.

As I explained in private earlier, I try to point people in the right direction, without giving recipes. Recipes do not constitute "understanding". Understanding comes only through study, experimentation, and at times a friendly hint from others.
There are too many people around who try to cream recipes from forums such as these in order to get into the market with their "own" designs quickly, without feeling the need to understand what they're doing. I don't feel any need to give these people a cheap ride by writing a "how-to" guide.

However, there are a few folks out here who themselves work and study hard to gain a proper in-depth understanding. There, it makes little sense to withold information. You yourself, for instance, will find out these things in due time anyway. So then I think it's worth to give nudges in the right direction, knowing full well that these hints won't be understood by people simply looking for a quick design help.
Yeah you know it's hard for someone in my situation to fully understand that fine line upon which you dance, even though I think I can.

Maybe in light of that next time just dont' say "I'm now withholding useful information..." just to make it easier on us?

All the same, yeah those leeches are around, I'd like to think anyone like that would fall on their face hard and fast. Like you say, there's only one way it can be done, it takes work.

I also appreciate that your hints usually are in the right direction as well. Usually.... well black gates are expensive anyway, I wont' even count that

I've dreamt of the same type of dead time control, maybe. Spent a few good hours researching that as well.

When you say negative dead time I'm thinking of predictive.... same thing?

The conclusion was very much like yours, but will remain in the back of my mind for later consideration. All the same I can't help but wonder what made _you_ classify it as being fairly impractical... was it the required reaction time for it to actually be functional? Still a good idea, if we are talking about the same thing.

It's almost looking like a waste of time to worry about dead time at all.

I trust we can ignore that Vth differs from device to device, thanks to a good manufacturing process.

So then we'd want to limite the rail current as we're playing with dead time .... so they'll be running cooler and have a higher threshold than they would in normal use... would you heat the devices externally to lower Vth closer to what it would be in normal operation?

It actually looks at this point like all one can do is tune it to be optimal at idle and hope for the best at higher output, where you're actually listening to it most of the time.

Lately I've just been concentrating my efforts on having the gate signals intersect at Vth, and at least in simulation this gives best results, and is the same as having zero dead time. With that relation in good form we dont' really need "dead time".... do we?

Seems like it's too much of a carry over from the digital only days.

Now if any of this is a song you can't dance to on here I'd appreciate if you late me know privately or whatever.


BTW Bruno, thought you'd get a kick out of knowing that since I moved at least 10 people have heard my little home brew UCD simple as can be version, only one i've built, and 10 jaws have dropped.

Best Regards,
Chris
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Old 30th June 2005, 06:52 AM   #22
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Quote:
Originally posted by classd4sure
Lately I've just been concentrating my efforts on having the gate signals intersect at Vth, and at least in simulation this gives best results, and is the same as having zero dead time. With that relation in good form we dont' really need "dead time".... do we?
Precisely. In its original meaning, "Dead time" is used to denote an intentional delay between turning off one FET and turning on the other, presuming gate switching time to be negligible compared to the intentional delay. This is typically true for designs that have optimal idle current. The delays we are looking at for normal use (higher idle losses, lower THD) are so much shorter that the FET switching time becomes dominant. Because of that, it makes little sense to try and distill a single figure. Even if you cross over at Vth, you will find distortion artefacts typical of dead time.
Crossing over at Vth is a practical proposition using P/N mosfets capacitively coupled to a shared gate driver, or less practical, using a drive transformer coupling all gates.
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Old 1st July 2005, 07:41 AM   #23
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Quote:
Originally posted by Bruno Putzeys

Most power FETs have metal gates. If they were polysilicon they'd be too slow for use in class D. The lead inductances form the limiting factor towards direct readout of the gate waveform. At realistic gate switching speeds (50-100ns), the fidelity of the waveform at the gate pin is still more than sufficient. Faster switching speeds make no sense if the dead time is long enough to be seen as a diode drop on the scope screen.

WHAT? METAL GATES??? what about vacuum tubes?

I'd say 99.999% of power FETs have poly gate. I am not aware of ANY power FETs still using metal gates. Most use low resistivity poly (aka silicide). All power FETs these days use self-aligned poly gate.

Faster switching speed reduces the time the FET is in saturation, where the switched node is half way between the rails, and the FET is dissipating a lot of power. The faster the better, but worse for EMI. You don't lose power for switching faster. Remember RC charging requires same energy regardless of its time constant.

All power ICs generates a good definitive blip, at least 20ns, as long as 60ns or more. Some even prefer longer than shorter, just so they sleep better. Enough said. No more free consulting.
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Old 1st July 2005, 09:08 AM   #24
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Hi,

the only metal gate mosfets in production I know are APT latest Series7 Mosfets. While there must be several tens of different devices in series, none are particularly suitable for class D, but mainly for several kilowatt SMPS.

Mest regards,

Jaka Racman
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Old 1st July 2005, 11:35 AM   #25
JohnW is offline JohnW  Hong Kong
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Quote:
Originally posted by tawen_mei
I'd say 99.999% of power FETs have poly gate. I am not aware of ANY power FETs still using metal gates. Most use low resistivity poly (aka silicide). All power FETs these days use self-aligned poly gate.
I agree with you, I've worked with a few larger MOSFET’s manufactures to help them understand the requirements of MOSFET’s for Class D, and NON use Metal Gate layers... although at times I wished they did....

A metal layer is used to distribute the Gate signal around the periphery of the MOSEFT die, with “fingers” distributing the signal into the die centre – however to maximize the RdsON vers Die area, the area spared for these “fingers” is limited.

Using a current probe on the MOSFET's Gate reveals some VERY interesting results.... I use ultra small current probes design for Laser Diodes....

John
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Old 1st July 2005, 11:55 AM   #26
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Hi John,

do you mean something like EMI sniffer probes from Bruce Carsten?

Best regards,

Jaka Racman
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Old 1st July 2005, 12:50 PM   #27
JohnW is offline JohnW  Hong Kong
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Hi Jaka,

No I don't use the interesting little "sniffer" probes you posted - but these (see attached PDF) - I find they have much better performance then there Spec sheet. I've had these for years - I'm sorry, but I have no idea who Made / Makes them as its not indicated on the Data sheet...

I once measured some SMALL 30V MOSFETs that required almost 300nS to be fully enhanced (until the Gate stopped requiring current). Turns out the manufacturer had a major issue with there polysilicon implantation process - could not implant within the “deep” trench... Due the the common measurement Spec. of 10% to 90% Rise / Fall time - the manufacturer had completely missed the fact that the last 5% or so of Turn-on was taking a lifetime... and when your normally looking at the first 20nS or so of the switching event - its easy to miss the VERY gradual slope over 300nS!!

Needless to say these devices had very poor THD performance (odd-order components).

Cheers,

John
Attached Files
File Type: pdf 711s current probe.pdf (81.6 KB, 72 views)
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Old 1st July 2005, 07:36 PM   #28
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Good info on MOSFETs, John. Thanks for sharing.

Jocko
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Old 1st July 2005, 09:36 PM   #29
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Quote:
Originally posted by tawen_mei
WHAT? METAL GATES??? what about vacuum tubes?

I'd say 99.999% of power FETs have poly gate. I am not aware of ANY power FETs still using metal gates. Most use low resistivity poly (aka silicide). All power FETs these days use self-aligned poly gate.
Ok, ok, my gig is making amplifiers, not FETs. But, since your point was to say that gate resistance was a significant factor, I wouldn't mind seeing a number stuck to that.
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Old 13th July 2005, 07:41 AM   #30
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If we couldn't read gate waveform, what can i do? Chip case e.g., looking to the totem pole waveform only? Especially, when rise/fall edges > dead time..
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