Nth Order Sigma-Delta

[Bruno Putzeys]

Now look here. I'm entirely happy to explain people how things work. I'm all for spreading knowledge. However, some folks go into the offensive to impress their own misunderstandings upon me. Sorry, if you can't ask questions, I'm not giving answers. I can only tell you your analysis is quite mistaken on both counts. Come back when you know how to ask questions instead of telling me that I'm wrong and that I'm missing things here and there.

If you believe your own version to be correct, well you can have it. There you go.

[digitoxin]

I don't want to impress anyone or wanted to be offensive. I have just posted my opinion, if i am wrong, i am happy to be corrected. I don't say that i am the owner of the only truth, what i posted is just what i notices based on my observations. I did some calculations regarding the Ucd thing and thats what came out, open for discussion.

digi

[Bruno Putzeys]

Cool, let's have a look.

1a) 2nd order self-oscillating deltasigma.
See attached drawing. The modulator has two poles at DC, one real zero before the intended switching frequency, two real poles after it.
Now look at the phase plot. As close as the phase shift gets to 180 degrees at low frequencies, it never gets there. It has only one crossover point at 180 degrees (here 133kHz). This is expressed as "second order loops are unconditionally stable". After an overload, the loop will always return to stable oscillation at the one and only crossover point.

1b higher order deltasigma modulators.
These modulators /do/ cross 180º at a lower frequency. Therefore, the modulator has two potential oscillation frequencies. However, for stable oscillation to persist, not only must the phase shift be 180º, also the loop gain must be unity. In this case, the "gain" is large signal gain. As you are undoubtedly aware, gain of two-level systems is inversely proportional to the amplitude of the oscillation as seen at the comparator inputs.
When the modulator starts up first, oscillation will start at the intended frequency. Once that is established, and because the attenuation of the two integrators is large at this frequency, loop gain is large. At the lower 180º point, therefore, gain is much higher than 1 and the system will be stable.
Now, when the modulator is overloaded (clipped) large signal gain becomes low, because the amplitude at the comparator is high. The integrators run away and instantly, gain is so low that the lower oscillation frequency becomes viable.
So, deltasigma modulators of order >2 start up stable, but are not unconditionally stable. They can shift to "unwanted" modes after an overload.

The problem is usually addressed by clipping the integrators, thus increasing system gain, preventing stable oscillation at the lower crossover frequencies. In this way, it's quite easy to build high-order systems that come back stably after overloads. I'm doing this as a matter of fact in discrete A/D circuits, where I usually employ 6th or 7th order modulators.

[phase_accurate]

I'm doing this as a matter of fact in discrete A/D circuits, where I usually employ 6th or 7th order modulators.

Do you set the clipping levels empirically ?

Regards

Charles

[Bruno Putzeys]

Second post because I haven't found out yet how to attach more than one file to one post.

2) UcD. Attached is the circuit and phase plot of the version known from the patent. I've purposefully left the output open, so you get the situation you were "worrying" (I doubt that) about.
As you can see, the phase lead network simply keeps the phase response above the 180º line. There is only one 180º crossover, which is exactly where I wanted it to be.

[Bruno Putzeys]

Originally posted by phase_accurate
Do you set the clipping levels empirically ?

Unfortunately, yes. At least in time quantised systems. As far as the actual signals are concerned, time-quantised deltasigma is a chaotic system elusive to modelling other than full-blown time simulation (or a practical execution).

When you're not working with time-quantised systems, you can indeed derive signal levels mathematically and set the clip levels thus.

[digitoxin]

Thanks for the extensive answers!

[Kenshin]

Does the "idle tones" noise comes from "periodic windows" in chaos?

Originally posted by Bruno Putzeys

Unfortunately, yes. At least in time quantised systems. As far as the actual signals are concerned, time-quantised deltasigma is a chaotic system elusive to modelling other than full-blown time simulation (or a practical execution).

When you're not working with time-quantised systems, you can indeed derive signal levels mathematically and set the clip levels thus.

[Kenshin]

Originally posted by Bruno Putzeys
I'm doing this as a matter of fact in discrete A/D circuits, where I usually employ 6th or 7th order modulators.

How many components would that need?

[Bruno Putzeys]

Originally posted by Kenshin
Does the "idle tones" noise comes from "periodic windows" in chaos?

According to some analyses (see James Angus, The Effect of Noise Transfer Function Shape on Idle Tones in Sigma-Delta Modulators, AES ppt 6450), yes.
What you find in practice when you make a plot of the 1st integrator output, you get a noisy "sawtooth" of which the frequency is dependent of the DC input (and equal to |fs*M|). What James found was that different choices of NTF (complex zeros or not) had a greater effect on the presence of these tones in the audio band than the mere difference in loop gain alone. I can't get my head around it yet, empirically, but there's no getting round his results.