My DIY UCD

[classd4sure]

Hi Sub,

No need to thank me for the thread it didn't cost me a dime

Those gate drive waveforms show the timing shift between the upper and lower drives due to capacitive interaction.

That it does, and I found that minimized with these values, it can be much worse.

With these values I can actually push the power up a good amount before shoot through becomes apparent, I'd bet the same could be done in a real circuit, as JohnW said the sweet spot has to be found. There needs to be a certain amount of overlap I believe, which should be fine as long as it is below threshold, and have intersection occur between 2.5 and 4V. The goal is of course to strike equilibrium between overlap and deadtime. This works best in simulation anyway.

However at some level certain measures need to be taken to beef up the driver and also parallel schottky diodes with the body diodes like I have in the full bridge version.

Neither one is of any concern at only 25V (or 35V) rails.

Regards

[classd4sure]

Hi,

Consider this a continuation of my previous post, the intent is to demonstrate the importance and usefulness of striking the previously mentioned "sweet spot" with respect to the gate drive signals.

It has taken a long time for me to figure this much out and I figure if anyone wants to attempt this circuit, or a similar one, it is need to know information.

With this circuit such performance is most easily attained by setting the comparators output current to a reasonable level, 3mA works great for me, then play with the ratio of turn on/off bias resistors, you can keep the series gate resistors rather low while doing this, 2 to 10 ohms let's say. You have some room to play with it before it affects that sweet spot you've found, but if you need to increase it beyond that and it messes things up, a slight increase in the turn on bias resistor should do the trick.

What you want to be looking at while doing this is the intersection point (aim for between 2.5 and 4V, 3 works good for these models) and slew of the gate drive signals (twice as fast for turn off), as well as the current through each mosfet. Once the current looks reasonable (no kilo amp spikes) then you're getting into the ballpark and power dissipation should be reasonable automagically.

You've already seen how nice the current though the output devices looks in my simulation at low power with 25V rails, now I prove my point with a demonstration at 50V rails and nearly max modulation. The increase of rail voltage is the only change made to the circuit I've posted in this thread.

I do hope this is found to be useful, and saves people the _many_ hours I've spent on it to get it this far. It was actually the biggest obstacle I've had to overcome with it, without doubt.

Yes, I'm aware Vth declines with increased temperature, so it stands to reason in a real circuit you'd want to optimize this at operating temperature... you'd have a hard time not doing that anyway

The 50V, incedently, is worst case for the IRF540 model, at 35V rails the max output will look very much like it does at 25V rails, with no current spikes at all.

I hope this makes some sense I've typed it up rather quickly.

First screen is all waves including power, next screen will better serve the intent of this post.

I hope this is helpful.

Regards,
Chris

[classd4sure]

.... you can see in the above screenshot that power dissipation has increased a fair bit from the simulation with lower rails, I think it shows ~0.5W dissipated in one of the prior screens.

The reason it has increased in a way related to the obvious increase in rail voltage, but more directly related to the mild current spiking. If the drivers were re optimized to remove that at this rail voltage and output level, dissipation would drop back down.

You see now how critical it is to find the sweet spot.

If this is off by just a little bit, shoot through and dissipation will be up into the Kilo range, resulting in a rapid smoke show, and maybe some fireworks too.

Regards,
Chris

[Kenshin]

IRF540Z? what's that?

[phase_accurate]

IRF540Z? what's that?

1.) http://www.irf.com/product-info/data...ta/irf540z.pdf

2.) most probably a very cool device indeed

3.) almost unobtainable from most distributors

regards

Charles

[classd4sure]

Hi Charles,

Actually Digikey has them in stock and they can be bought in single or small quantities, I was thinking of trying a few on my next project (which.. is this thread's circuit) to see how they compared to my fairchild devices.

Regards

[phase_accurate]

I have been comparing the datasheets of the various 540 versions. The Z version excels in terms od rdson, current handling and diode recovery time but dV/dt isn't specified at all.
The N version has the least reverse transfer capacitance and the best dV/dt specification. Regarding current handling and rdson it is inbetween the other two types.

Regards

Charles

[Bruno Putzeys]

dV/dt capability is slightly compromised when the device is fully optimised for Qrr but usually it's still more than good enough.

[phase_accurate]

Bruno

Have you done any experiments with these already ? Or don't you like IR at all ?

Regards

Charles

[Bruno Putzeys]

Originally posted by phase_accurate
Bruno

Have you done any experiments with these already ? Or don't you like IR at all ?

Regards

Charles

I must admit I've been completely ignoring IR FETs for the past 4 years because all that time they've been way behind on the rest (Fairchild and Philips mainly). So yesterday evening I was reading this thread and looked up the irf540z and was very surprised. Seems IR is catching up and I seriously need to try out some of these new devices.