Delta-Sigma Class D

[contitek]

Hi Guys,

Quick question and no Bull..
Anyone has done a working classD with Delta-Sigma.
Much more than a tiny-viny cellphone amp ?
Ohh Yeah!-Like hundreds of watts ??
No theoretical bull....... please!
I do know all of that.-Thanks alot!
Did you or did you not ??
I'm more interested of the output filter and the EMI performance of it.
Again dont give me lecture about how the hell should I do this and that.
If you made it work you're my guy!
Let me know please!
Thanks!

[phase_accurate]

Since you seem to know everything I wonder why you ask questions at all ???

Aaaaaah....... There is that question about EMI and the output filter !
No DIYer cares about EMI of his class-d amps. If we do neither interfere with our familiy members' or neighbour's radio/TV/pacemaker/.... or when we don't take any planes from the skies we are quite content with the EMI performance.

I do therefore assume that you want to get FREE info for the development of a COMMERCIAL product, don't you ?

Regards

Charles

[DonoMan]

ZING!

[John Hope]

Hi Charles

I would also throw in the old maxim "Theory without Practice may be pointless, but Practice without Theory is BLIND". It is not possible to properly design something unless one understands how it works.

If we're talking all-digital (PowerDAC) amps, the only 'serious' all-digital SigmaDelta amp I'm aware of is the one by Sharp. (This is the one that looks like a mantlepiece ornament out of Shogun. . .) The tech details Sharp give on this amp are inscrutable to say the least. On the specs I've seen they rate it at 100W and infer the output switching frequency is 64fs. I seem to recall Sharp stating they used a 6th or 7th order noise shaper, which would be appropriate (just) for 32fs or 64fs.

Even if you use the new Philips 'no dead time' monolithic output stage or those new purpose designed IR mosfets for Class D (IRF66??), the switching losses at 64fs would be prohibitive.

My guess is that they are using a noise shaper with a 'bit-flipping' strategy of the kind devised by Mark Sandler and his various postgrads in the late 90's. (There's an AES paper on it which may be bought from the AES online shop). Sandler's scheme achieves a reduction in the number of output transitions by deliberately 'misquantising' and flipping the noise shaper output state in order to increase the runlength of the output bitstream. Sandler's objective was implementation of this scheme in an FPGA.

Personally I see no advantage to be gained from SigmaDelta over PWM for PowerDAC conversion. The inherent non-linearity of PWM can be precompensated and I would imagine that the higher fs of SigmaDelta would only exacerbate EMC problems.
Significantly, in another AES paper of the mid-90's Lars Risbo developed an all-digital SigmaDelta amplifier that I seem to recall switched at 32fs, and found the efficiency was disgusting. Lars, who went on to found Toccata and design the TacT Millenium, gave up SigmaDelta in favour of PWM.

I would be very interested to hear if anyone has more meaty technical details on how the Sharp 1-bit all-digital amp works. . . .

Best wishes


John Hope

[phase_accurate]

I would be very interested to hear if anyone has more meaty technical details on how the Sharp 1-bit all-digital amp works. . . .

Not exactly but

1) Bruno once mentioned some details like that they were using switched capacitor integrators and that the whole amp was an EMC mess.

2.) You can find a lot of patents by Sharp regarding delta-sigma amps and also delta-sigma modulators per se.

The product info from sharp themselves and some magazine reviews say that the amp...

...uses a 7th order loop at 2.8... Ms/s (newer verisions even twice this sampling rate).
... Output topology is a full-bridge using IRF540 and a fourth-order lowpass @ 100 kHz (the newer incarnation with 200 kHz) and pre - filter NFB.

I think an SD amp should at least use 4 Ms/s to achieve good performance but then you would have an idle switching frequency around 2 MHz. But the switching losses should drop as soon as there is an input signal present.

Regards

Charles

[Jaka Racman]

Hi John,

While I can not comment on Sharp design, there is a very interesting design by Bruno Putzeys that solves efficency problem. Here is patent and here is AES publication: A True One-Bit Power D/A Converter, AES convention 112, April 2002.

Best regards,

Jaka Racman

[John Hope]

Thanks Jaka.

Charles:

I tried a 4th order BW LPF (50kHz) on one of my early PowerDAC protos - there's a pic of it attached - and although output ripple was very low, it sounded a bit 'tight' and image location was poor, probably due to the non-linearity of phase. But I guess if the passband is extended to 100kHz or 200kHz, the phase over the audio baseband is probably linear enough.

The issue of feedback around the power stage - or even overall feedback - applied to all-digital power amps is one which occupies much of my hobby thoughts nowdays and I may start a new thread on this issue.

Chhers


John Hope

[phase_accurate]

There is a B&O patent dealing with that. They vary the timing of the rising and falling edges of a power DAC according to the deviation between ideal and actual waveform.

In such a topology it would be difficult however to take NFB after the LC filter. But at least the phase-shift problem could be accounted for in advance in an all-digital solution.

But I am still convinced that DA conversion can be done most precisely with low voltage/power and amplification can best be done in the analog domain. So let's build these DAC-fed analog class-d amps !!

Regards

Charles

[Jaka Racman]

Hi,

John Westlake is undisputedly master of the feedback around the power stage. As I understand, in some months time his designs will become comercially available under very reasonable conditions (his own brand).

Now this will be embarassing for John who is a very modest man, but here is a quote from www.classD.org (which also was first to report about UcD):

I should mention one dramatic new entry. On the www.diyaudio.com forum there's a chap called "JohnW" who is posting distortion measurements of a "digital" amplifier sporting <1ppm (!!!) distortions. Like he came down from the future to show us how class D is being done in 2020.

It seems that we will soon be faced with new benchmark design in digital domain, like it is now hard to surpass UcD in analog domain.

Best regards,

Jaka Racman

[John Hope]

Hi Charles

I suspect the patent you're referring to is by Karsten Nielsen for a system which he calls 'PEDEC'. Nielsen has connections with B&O. In Nielsen's scheme the PWM signal at the bridge phase node/s is scaled and compared with a reference derived from the TTL level PWM from the modulator output, and the error signal so derived is used to in a closed loop to re-slice (within a window of limits) the PWM.

Last year I breadboarded an experimental PEDEC system based on this and tested it out on my PowerDAC 1 amplifier, now used as a test bed for various atrocities. I was able to compensate the PEDEC loop to be stable with the sense signal taken after the amp's output filter.
The uncorrected THD+N of my PowerDAC is around 0.15% (any dBFS, 20-20kHz, up to 136W rms into 8R, measured IEC A) and this was reduced to 0.04% with the correction system. (The 'raw' THD+N from the TTL level PWM measures 0.02%, which is consistent with that expected from the 3-point/frame PWM linearisation scheme used.)

While this was encouraging, I found the reslicing system prone to noise and on my particular PowerDACs, as with the TacT, it worked out quite complex because of the need to obtain a constant amplitude sense signal from a power stage fed with an adjustable supply rail. (I used two SSM2018 VCA's; one as a supply voltage tracking servo and the other as a scaling VCA).

So looking objectively at this PEDEC potpourri of mixed signal stuff I though Sheeeeessssh... This is not the way to go; there must be a better way. So I'm still open loop and still looking and thinking . . .

Cheers


John Hope