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Peter_ma 23rd February 2005 07:35 PM

How eliminate offset voltage in my design
2 Attachment(s)
I just make a simple class D amp.
But their is always an offset voltage(7V) at output A and output B.
This make me sad.

What way can I eliminate this offset?
Or...may be my design is wrong?
Or ...need make a change on any part of the circuit


schematic attached

****two waveforms at output A,B ********

classd4sure 23rd February 2005 08:30 PM


I think you're design is a little off.

L1 and C3 is a filter for one half of the bridge, and connected properly. Then you've got your load connected from that, directly to the other side of the bridge, and there's your mistake.

R3, your load, should instead connect to the node in between L2 and C4, this way it is filtered from both sides of the bridge.

Good luck,

Centauri 24th February 2005 01:26 AM

Apart from the mistake in the output filter in the circuit, this offset is perfectly normal due to the single-ended supply. The important thing is that there is no offset BETWEEN the two output pins. With a full bridge setup, neither output will be zero.


classd4sure 24th February 2005 05:01 AM

Ah yes that's a good point.

However it could all be referenced to a negative rail instead of ground, which would put the outputs near ground potential instead vsupply/2.

I think this method is prefered for safety reasons, the outputs don't sit at a high voltage. Other than that though either way works.


Jaka Racman 24th February 2005 07:50 AM

Hi Chris,

Your idea would complicate control circuit a bit. With zero signal, both lower fets should be on all the time. With input signal, one leg would stay on all the time while on the other duty cycle of lower fet would be decreased from 100% to 0%. This would require two PWM comparators and offseting ramp or reference signal for each one. The main problem I see is crossover distortion at small input signals if run open loop.

But there are some designs using above control metod in PFC circuits, where you can get rid of input bridge rectifier.

Best regards,

Jaka Racman

Peter_ma 24th February 2005 12:13 PM

2 Attachment(s)
Previously I drew a wrong schematic.Chris remind me. Thanks.

This one is my orgainal schematic. I tried to draw it more clearly.

I consider all opinion and make any possible trial.

And tell you later.

I wait any futher opinion.


Peter_ma 24th February 2005 12:13 PM

2 Attachment(s)
The output A and B

Jaka Racman 24th February 2005 07:43 PM


as you were told before, your signals look like they should. It is perfectly normal that they operate like that. All full bridge designs do the same. Why do you consider offset to be the problem?

Best regards,

Jaka Racman

subwo1 24th February 2005 08:09 PM

Hi Peter_ma, I was wondering what the DC potential between your speaker terminals is. The best way I know to eliminate the chance of it is feedback referenced to a fixed point between power supply rails.

subwo1 25th February 2005 03:07 AM

And I am wondering if there is a little bit of DC on the speaker is is such a thing readily or practically addressable, feedback or not.

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