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Old 21st February 2005, 05:20 AM   #1
Pierre is offline Pierre  France
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Default Mosfet reliability in Class D amplifiers

Hello all.
This thread is a continuation of "Help with feedback", which I started months ago. It has derived in a interesting question that worths the pain we treat separately.
When testing some of my amplifiers, some of them have failed due to shorted mosfets.
Some of the members point to avalanche phenomena, others to the body diode and excessive dV/dt in unrated devices.

"analogspiceman" proposes that the dV/dt rating in repetitive avalanche mode is not given in all the mosfets, particullarly one of the ones I am using, NTP35N15. However, he said that FQPP46N15 is rated at about 6V/ns, although I can't find this data in the datasheet. However, a pair of them have also failed in the same way. Where did you find that value?

Others propose layout as the main cause: some bouncing can trigger false conduction and hence instant failure of both devices.

Any ideas are welcome.
Thanks.

Pierre
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Old 21st February 2005, 08:41 AM   #2
Pierre is offline Pierre  France
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Peter, I can't find info on the mosfet you previously used, the ones you say that worked very bad. What was the problem with them, did they overheat or simply failed in a similar way as mine?

BTW: the mosfets you say you use are TO247, but the photos you posted show TO220 mosfets, what are them?

Best regards
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Old 21st February 2005, 12:13 PM   #3
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Pierre,

I had problems with getting a clean gate drive waveform, which resulted in shoot-though etc. They died in a much more spectacular fasion i think, they totally exploded =) .

Yep, very observant of you, they are actually the same mosfet, just in different packages. I opted for the TO-220, as it was a bit smaller, but has a lower peak power disipation rating as expected, in my situation this wasn't a problem.

Regards

Peter.
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Old 21st February 2005, 01:04 PM   #4
Pierre is offline Pierre  France
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You had a worse gate waveform with the other mosfet but the same layout? Perhaps that had a bigger Qgate?

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Pierre
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Old 21st February 2005, 01:17 PM   #5
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I don't think they did, it might have been more to do with the Millar charge. I am not sure though, also the output slew rate was quite slow in comparison.


I had a fair bit of trouble keeping the fets cool as well, at frequencies above 30 or so kHz.

Peter
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Old 22nd February 2005, 07:33 AM   #6
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Hello,

I posted this already but It seems to be the best app note going on this topic, well explained and even providing worked examples to evaluate repetitive avalanche SOA.

Here's the link again:

http://www.semiconductors.philips.co.../AN10273_1.pdf

I've seen it written by someone who knows alot about how to handle mosfets that the zener drain-gate feedback technique can be troublesome with fets rated at greater than 100V, because the parasitics of the devices in that range lead to oscillation well into the Mhz range, and you wind up with greater than 20V on the gate, causing spurrious turn on.

Ever seen this problem? Of course I'm not sure how relevant that is because of the always advancing technology..

Regards
Chris
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Old 22nd February 2005, 01:41 PM   #7
Kenshin is offline Kenshin  China
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Quote:
Originally posted by analogspiceman

Keep in mind that the reapplied dv/dt limit is never exceeded by too strong of turn off drive (one need only limit the turn on drive). This is best done with a simple dv/dt feedback circuit from drain to the appropriate spot in the gate drive. Simply increasing the gate resistor will serve to limit maximum dv/dt, but it also slows down the already slow enough parts of the transition, thereby unnecessarily increasing switching losses.

why strong turn off never exceed the dv/dt limit?
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Old 22nd February 2005, 03:31 PM   #8
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Quote:
Originally posted by analogspiceman
Keep in mind that the reapplied dv/dt limit is never exceeded by too strong of turn off drive (one need only limit the turn on drive). This is best done with a simple dv/dt feedback circuit from drain to the appropriate spot in the gate drive. Simply increasing the gate resistor will serve to limit maximum dv/dt, but it also slows down the already slow enough parts of the transition, thereby unnecessarily increasing switching losses.


Originally posted by Kenshin
Why would strong turn off never exceed the dv/dt limit?
One should never say "never", but the mosfet dv/dt problem generally only occurs in a totem pole structure where one of the mosfets' body diodes is first conducting substantial current at the end of dead time and then is immediately (i.e., before it fully recovers) forced, by sudden turn on of the other mosfet, to support too much voltage too quickly, thereby inducing a destructive secondary breakdown in the parasitic bipolar/diode region of the mosfet. Turn off drive speed to the totem pole's "passive" device simply doesn't matter because its voltage is pinned by the current flowing in the reverse direction through its own body diode.
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Old 23rd February 2005, 10:38 AM   #9
Pierre is offline Pierre  France
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About the power section schematics I posted. Someone asked why I had a shottky diode in parallel with the the low side mosfet and not in the upper side one.
It is there to protect the driver from negative spikes at VS output (referred to COM pin, which is connected to the upper leg of the current sense resistor) If I remember well it is recommended in the IR2110 datasheet or some app.note.

Is it bad placed there?

Have you guys found any other thing worth reviewing or modified? In particular, I think it is ok to connect COM pin to the upper leg of the current sense resistor instead of VSS, as it is there where the source of the LS mosfet is connected, right?

Best regards,
Pierre
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Old 24th February 2005, 11:20 PM   #10
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Default FET Drive

I'll give you a hint on what the big guys use. They have a PNP transistor between gate and source to discharge the gate source capacitance faser, hence shutting off the FET faster. This makes it run cooler.
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