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Old 12th February 2005, 01:37 PM   #1
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Default Mosfet Shifting Vth by Coil Current


The following observations are based on simulation, I'd like to know how they differ from reality.

In simulation it seems Vth of the mosfets varies in amplitude according to the inductor current, further delaying turn on. This appears to be more troublesome in full bridge, not that it's any worse than with a half bridge, just that it may have more destructive results, due to shoot through forming accross the bridge.

I believe this timing error is in no way related to the timing of the gate signals themselves, they are in perfect synch.

It of course occures equally on both high and low side drivers, alternating between the two dependant on output, so this is different than the previously discussed regenerative effect seen on the high side switch.

I've seen it shift the threshold by as much as 4 volts, as seen by the plateau level on the gate signal, and the actual slew across the device.

I'll follow this up with some visual examples if required to further clarify the problem.

So, is this due to poor device modeling or could one expect this to occure in a real world circuit as well.

I haven't seen this mentioned in any app notes, or maybe it is there and I just glanced over it in my hunt for other knowledge.

The models I'm using are advanced analysis pspice irf540's, sub circuit based.

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Old 12th February 2005, 06:42 PM   #2
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Hi Chris,

Here is Bruno's explanation:

Note: The plateau voltage is simply the gate voltage corresponding to the drain current flowing at that time. The rule is simple. As long as a MOSFET is not in saturation, Vgs and Id are linked 1:1 as per the Id/Vgs graph in the data sheet.

Once you get that firmly locked inside the head bone, you can "read" Id from the gate voltage. I never bother to directly measure drain currents. The gate tells me all I need to know. I hope/expect this is what mueta relies on in their chip.

Here is the link to the whole post.

Best regards,

Jaka Racman
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Old 13th February 2005, 05:19 PM   #3
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Hi and thank you for the reply.

The graph which I believe Bruno was refering to the in datasheet, of drain current Vs gate-source voltage, doesn't seem to answer this question as it only shows drain current being a controlled as a function of Vgs.

Basically what's happened is that I've rediscovered the miller effect for inductive switching.

I see in some data sheets, the gate charge Vs gate-source voltage is given with a fixed VDD and varying drain current, but only for a few discrete levels of drain current, say 12 and 24A. While in others, it is given with fixed drain current and a few different VDD levels.

In the one which varies with drain current it shows a slight increase in the plateau level's amplitude for the higher current, say ~.25V, and that's for a doubling of drain current, from 12A to 24A. This seems to show that drain current does indeed affect plateau level, and it stands to reason an inductive load would amplify this as the gate driver in effect has to "fight" against the inductor, via Crss. It however doesn't seem to show it being anywhere near as bad as simulation would indicate, where the plateau level doesn't occur until another ~4 volts Vgs above the usual level.

It seems that while a self oscillating amp is a good solution for self correcting these induced timing errors, it is of course no benefit to the sloppy switching itself.

I realize other dynamic factors come into play as well, so I cant' say with certainty if this effect would really be better in reality than simulation indicates, and that's really what I was hoping for a comment on.

I will be researching this further.

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