Nth order noise shaping

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I here present a scheme that can be used for Nth order noise shaping suitable for Class D amplifier feedback.
In the example here, I’ve made a 4th order feedback, but more blocks can easily be added or removed.

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The cut-off frequency is controlled by the ratio between the four capacitors and R6, R8, R9 plus R10.

The ratio between R6, R8, R9 and R10 controls the poles. I have not optimized the ratio. By doing so, it’s possible to get a flat output magnitude and phase response.
As long as the opamp open loop amplification is large, this resistor ratio has no influence on the order of feedback. Only stability and the magnitude ripple around cut-off will be affected.


Opamp U1 dominates the noise generated by the feedback system. Therefore only one low noise opamp is necessary to construct an outstanding feedback system.


Bode plot
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FFT analysis
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I've olso made good progress in making feedback after a 2nd order LC output filter. I'll write a post about this later. Happy noise shaping.
 
It shouldn't be too difficult to take NFB from an output filter even with SD (I wonder why Sharp didn't do it).

At what sampling frequency do you want to run it ?

I am aware that this topology here is the one that makes it easier to take an output filter into account.
OTOH I like the loop topology with only one feedback path because you would have to change only one resistor if you want to adapt for different supply voltages.

Be aware that you might need much better noise suppression in practice than theory predicts (just think of that Sharp amp with a 7th order modulator that only achieves 100 dB of SNR).

Have you ever run it as a discrete-time model (like the one that I posted within the "Analog devices thread"). Since my version of SPICE is very limited I did have to use a trick to do it.

Regards

Charles
 
A few quesitons though.... Are there 7 opamps used in that diagram??

Yes, the opamp usage i 7, but I'm sure that it's possible to modify the configuration so that all the inverters can be avoided or reduced. I might look into that.

Have you tried simulating using 'real' component models?

The opamps have a gain of 1E6 and are limited to a -/+15 supply. As far as I know the model dosn't contain slew rate, GWB nor poles.
Resistors and capasitors are linear and they have no deviation.


It shouldn't be too difficult to take NFB from an output filter even with SD (I wonder why Sharp didn't do it).
It's reasonable easy cancel out poles in a LC filter and make feedback possible. But if you take deviation and different load conditions into account (no load, 1ohm or 8ohm), stability and plenty of feedback becomes hard to achieve. Also the load might contain complex components at high frequencys, which gives you more poles that those you've taken account for.

At what sampling frequency do you want to run it ?
This is only a model of the analog feedback system. But I'm working on a 350kHz Class D. For that I want to make beedback up to arround 125-150kHz (Neuquest allowes 175kHz in theory, but getting to close to this frequency gives aliasing = added noise)

... only one resistor...
You might have a point there. On the other hand, changing the supply voltage eg. with a factor 1/2, only worsen the feedback with 6dB, witch is almost nothing. You really have to make a big change in supply voltage, for this to be a real matter. B&O ISEpower change their supply voltage with a factor 10, when the signal is detected low. This 20dB factor, with accounts for a change in the feedback path. Therefore they have done so.
If you want to change to feedback often anyway. You could place a noninverting amplifier first in the feedback path and use it's gain to compensate for different supply voltages. This can be done with only one resistor.


Sharp amp
100dB SNR is good I think, but 7. order feedback sounds like a lot. Maby they should increese the switching frequency and also work on open loop noise sources. Looking into the ratio between MOSFET Ron and Cds ratio, it's fairly to go for a high Ron (50mohm+) and the enclosed low Cds, with respect to P losses. With the right ratio, theres fairly no difference i loss between 100kHz switching and 400kHz.


Have you ever run it as a discrete-time model
No. I don't know much about how to do so.
 
Do I get it right that you want to use PWM and not delta-sigma then (because you are talking of a switching frequency of 350 kHz?) ?

You could place a noninverting amplifier first in the feedback path and use it's gain to compensate for different supply voltages. This can be done with only one resistor

I must admit that I didn't think enough. You are right in that the circuit can be rearranged that only one resistor has to be changed in order to adapt for different voltages. But please do it passively and don't use active components in the feedback branch.

I once tried the topology intended to be used as SD modulator, as a feedback network for a PWM amp (on the simulator only), and the results looked indeed promising.

Regards

Charles
 
If you have a PWM modulator with good linearity you would not necessarily need such a high order of NFB loop (though in simulations at least one can achieve fantastic THD values).
you would not need to remove the carrier signal completely either.

And yes, also a delta-sigma amp would show some switching residual. The difference is that the SD amp's residual is noise-like (see attached simulation) and the PWM's resembles something like a distorted sinusoidal.

Regards

Charles
 

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I'm very pleased to se that the delta-sigma converter dosnt switch every clock cycle (I'm assuming that you gate the digital signal through a d-flip-flop). This could really lead to a huge improvement in MOSFET efficiency. U^2*C*f losses are large when you go for a low Ron. Less switching is needed in order reperesent a signal. However, I'm afarid that less cycles will be skipped, when the amout of feedback is increased and there by no efficiency benefit of the delta-sigma converter. What do you say?
 
It does indeed lower the pulse-repetition frequency with increasing input voltage. OTOH it also has a high IDLE switching frequency which can also lead to problems.

Just a remark: Because I ran into limitations when doing mixed signal simulations I just use a S&H and a limiter instead of a comparator and D-FF.

Regards

Charles
 
Incredible!

How did you arrange the open loop poles / frequency response to stabilize it ?

Noise shaping above 3th order implemented by cascading many integrators have stibility problems. And pratical high order D-S ADCs usually use MASH technology instead -- parallel several 1st order modulator together and cancel some noise.
 
High-order noise shapers do indeed have stability problems. They are not per-se instable however. They run into stability problems as soon as the quantiser is overloaded.
In the thread starter's case (usage of this loop topology for a PWM amp) this would only happen in case of clipping, i.e. it would show ugly clipping behaviour without addditional measures.

Since a "one-bit SD" modulator is always in an overloaded state measures have to be taken to avoid instability for these.
One possibility is the MASH architecture that you mentioned (although not very practical for an amp but maybe I am wrong) or the detection of instability and therefore triggering an integrator reset and last but not least the oldest method: use of clipping in the integrator stages.
I used the last one just for simplicity. It is important that the last integrator is the first one to clip (in the forward structure that I use) and the first one is the last one to clip. The actual clipping levels are important for the performance. I did not care about that (all of them clip at +- 5 Volts peak) and therfore the performance is not as high as one would expect from a fourth order modulator with a sampling rate of 4 Ms/s. So I only have an SNR of 80 dB approx @ 20 kHz instead of the theoretical 179 dB. While these 179 dB could never be achieved in practice, better than 80 dB should still be possible.

Regards

Charles
 
why always overloaded?

Because it always shows the highest or lowest level it can represent, never something inbetween - that's the main difference to multibit delta-sigma.

btw: is it possible to use RC passive integrator to avoid overflow?

This kind of modulator would indeed be difficult to overload but it would not have enough "forward gain" in order to be effective.

In my topology only one integrator is a "real" one, i.e. the classic inverting integrator. All the subsequent ones are first-order lowpass filters followed by a non inverting gain-stage. This way the number of op-amps could be kept to a minimum.

Regards

Charles
 
Clipping in the integrators removes information form the signal and it's not preferred. One way to get arround this is to cancel out the integraters when they clip and there by reducing the feedback to a lower order. I've read a couple of papers describing this, but never seen it implented.
Another way to get arround it would be to place a limiter, before the input of the whole system and thereby avoid clipping. However it might not be possible to create a limiter with sufficient low distortion (a limiter is in nature nonlinear).
 
How did you arrange the open loop poles / frequency response to stabilize it ?

If you look at these two integrators
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Their gain is
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Which means that we have a second order inverting integrator. However when w->0 then A(w)->infinite which is not possible. Actually A(w)->Aopen_loop
Then the gain suddenly becomes noninverting and you'll get positive feedback and oscillation.
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Maby this is what youve experinced.

Before you start thinking about poles, you'll need the right topology. The one I've demostrated in this thread dosn't suffer from the problem presented here.
 
While these 179 dB could never be achieved in practice, better than 80 dB should still be possible.

For sigma-delta systems linearisation can be achieved by dithering the modulator
with random noise injected at the input to the quantiser.
Normally you'll get idle tones arround sertain frequencys. You can avoid this and get a better SNTR by adding a little bit of noice.

This might be of interest
Psychoacoustically Optimal Sigma Delta Modulation
http://www.scalatech.co.uk/papers/jaes497.pdf

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