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Old 9th February 2005, 03:31 PM   #11
sovadk is offline sovadk  Denmark
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I'm very pleased to se that the delta-sigma converter dosnt switch every clock cycle (I'm assuming that you gate the digital signal through a d-flip-flop). This could really lead to a huge improvement in MOSFET efficiency. U^2*C*f losses are large when you go for a low Ron. Less switching is needed in order reperesent a signal. However, I'm afarid that less cycles will be skipped, when the amout of feedback is increased and there by no efficiency benefit of the delta-sigma converter. What do you say?
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Old 9th February 2005, 03:58 PM   #12
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It does indeed lower the pulse-repetition frequency with increasing input voltage. OTOH it also has a high IDLE switching frequency which can also lead to problems.

Just a remark: Because I ran into limitations when doing mixed signal simulations I just use a S&H and a limiter instead of a comparator and D-FF.

Regards

Charles
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Old 14th February 2005, 08:16 AM   #13
Kenshin is offline Kenshin  China
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Default Re: Nth order noise shaping

Incredible!

How did you arrange the open loop poles / frequency response to stabilize it ?

Noise shaping above 3th order implemented by cascading many integrators have stibility problems. And pratical high order D-S ADCs usually use MASH technology instead -- parallel several 1st order modulator together and cancel some noise.
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Old 14th February 2005, 09:26 AM   #14
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High-order noise shapers do indeed have stability problems. They are not per-se instable however. They run into stability problems as soon as the quantiser is overloaded.
In the thread starter's case (usage of this loop topology for a PWM amp) this would only happen in case of clipping, i.e. it would show ugly clipping behaviour without addditional measures.

Since a "one-bit SD" modulator is always in an overloaded state measures have to be taken to avoid instability for these.
One possibility is the MASH architecture that you mentioned (although not very practical for an amp but maybe I am wrong) or the detection of instability and therefore triggering an integrator reset and last but not least the oldest method: use of clipping in the integrator stages.
I used the last one just for simplicity. It is important that the last integrator is the first one to clip (in the forward structure that I use) and the first one is the last one to clip. The actual clipping levels are important for the performance. I did not care about that (all of them clip at +- 5 Volts peak) and therfore the performance is not as high as one would expect from a fourth order modulator with a sampling rate of 4 Ms/s. So I only have an SNR of 80 dB approx @ 20 kHz instead of the theoretical 179 dB. While these 179 dB could never be achieved in practice, better than 80 dB should still be possible.

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Charles
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Old 15th February 2005, 07:11 AM   #15
Kenshin is offline Kenshin  China
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Quote:
Originally posted by phase_accurate
Since a "one-bit SD" modulator is always in an overloaded state
why always overloaded?

btw: is it possible to use RC passive integrator to avoid overflow?
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Old 15th February 2005, 08:08 AM   #16
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Quote:
why always overloaded?
Because it always shows the highest or lowest level it can represent, never something inbetween - that's the main difference to multibit delta-sigma.

Quote:
btw: is it possible to use RC passive integrator to avoid overflow?
This kind of modulator would indeed be difficult to overload but it would not have enough "forward gain" in order to be effective.

In my topology only one integrator is a "real" one, i.e. the classic inverting integrator. All the subsequent ones are first-order lowpass filters followed by a non inverting gain-stage. This way the number of op-amps could be kept to a minimum.

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Charles
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Old 17th February 2005, 08:08 PM   #17
sovadk is offline sovadk  Denmark
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Clipping in the integrators removes information form the signal and it's not preferred. One way to get arround this is to cancel out the integraters when they clip and there by reducing the feedback to a lower order. I've read a couple of papers describing this, but never seen it implented.
Another way to get arround it would be to place a limiter, before the input of the whole system and thereby avoid clipping. However it might not be possible to create a limiter with sufficient low distortion (a limiter is in nature nonlinear).
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Old 17th February 2005, 08:28 PM   #18
sovadk is offline sovadk  Denmark
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Quote:
How did you arrange the open loop poles / frequency response to stabilize it ?
If you look at these two integrators
Click the image to open in full size.
Their gain is
Click the image to open in full size.
Which means that we have a second order inverting integrator. However when w->0 then A(w)->infinite which is not possible. Actually A(w)->Aopen_loop
Then the gain suddenly becomes noninverting and you'll get positive feedback and oscillation.
Click the image to open in full size.
Maby this is what youve experinced.

Before you start thinking about poles, you'll need the right topology. The one I've demostrated in this thread dosn't suffer from the problem presented here.
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Old 18th February 2005, 02:31 PM   #19
sovadk is offline sovadk  Denmark
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Quote:
While these 179 dB could never be achieved in practice, better than 80 dB should still be possible.
For sigma-delta systems linearisation can be achieved by dithering the modulator
with random noise injected at the input to the quantiser.
Normally you'll get idle tones arround sertain frequencys. You can avoid this and get a better SNTR by adding a little bit of noice.

This might be of interest
Psychoacoustically Optimal Sigma Delta Modulation
http://www.scalatech.co.uk/papers/jaes497.pdf

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Old 18th February 2005, 02:52 PM   #20
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I AM using dither !
One of the reasons for the result is the usage of SPICE for discrete-time simulation. There seem to be better tools for that purpose.

Regards

Charles
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