Charles, we need your help on feedback in single supply Class-D

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subwo1 said:
Looks almost identical to a small signal transistor common emitter circuit with about a 10K ohm pull-up on the collector.

Yup, good eye. It's the basic 2 transistor mosfet driver posted earlier, as seen on the UCD patent etc.

1.2K pullup (100 Ohm in series with the gate), 600ohm turn off resistor, and driven with about 2mA from the comparator, VCC 15V.

Nice note about the optocoupler method.

All this driver talk might have been better off in one of the driver based forums, but as a classd reference thread, it's all on topic :)
 
Ah yes, thanks. That driver output waveform is interesting. It does rise very slowly, more so than I would have expected. I guess that is why it switches the MOSFETs very smoothly and why MOSFET selection is critical.

The optos I mentioned could not produce anything close to UcD quality because they are not linear but behave more like TTL, I guess. I do hope to try out the H11Fx bidirectional FET output opto as a level shifter in a classD amp sometime, since it is linear and rated almost as twice as fast as a bipolar output type.
 
phe waveform, the rise time (500ns) is way too long. Is that from simulation or actual scope capture?

Haven't seen the schematic of the circuit you guys are talking about, but I'm hearing 1.2Kohm pull-up, 600ohm pull-down, and 100ohm gate resistor. These figures are excessive!!! How much dead-time are you running with? what kind of efficiency are you getting? what about THD? Typically the rise/fall time for a 500KHz switcher is <50ns, and more like 25ns...

Driver pull-down strength should be <3ohm. If it's too weak, to cut the story short, the weak pull-down can't keep the FET off when the switched node is slewing. Pull-up strength is a compromise of EMI and effienciency (and THD in class-D amps). No gate resistor should be needed; if you have ringing/EMI, that means you have layout problems. You may try to limit the pull-up strength somehow, but only without introducing additional impedance in series with the gate. The FET's parasitic gate resistance (>1ohm) and inductance (1nH) is already bad enough you don't need to add more.

That said, you should not be using anything bigger than SO-8 FETs. Okay, DPAK is absolutely the limit. The inductance in those TO-220 packages prevents any switching at serious speed. If you try, at best it runs hot, typically it will run for a second and the package will smoke or explode in your face (depending on the up-stream power supply).
 
Hello tawen_mei. I hope you enjoy the forum.

My ramblings seem to have foundation in my lack of complete equipment, being a lowly DIYer. I work from the perspective that I probably will never get beyond point to point wiring for the most part. I made a couple simple circuit boards in the past, and the experience produced minimal satisfaction. Much of the reason is that I end up being satisfied with a design for only a little while before I am into total redesign. I'd say that if a project is going to work p2p for me, it probably will work on PCB if I ever get that far. I just build for personal projects, so haven't the attraction to the professionalism requiring boards.

Well, now that I have exposed all that craziness, I must say that I see a lot of good, logical comments in your post. I was surprised that one of my projects had very short high frequency power loops, using SO-8 output MOSFETs, 30 ampere peak capable MOSFET drive, quick turn-off but half as fast turn-on, but I still was dissatisfied with EMI. Since shielding seemed to make no difference, I found it interesting that I could not get EMI filtering to make a worthwhile improvement either. So, instead of going for PCBs, I decided to go back to the drawing board until I can start a new season of work in the shop.

Well, the one thing I guess I take seriously is the DIY part of the whole thing. All my work hinges upon that idea.
 
tawen_mei said:
phe waveform, the rise time (500ns) is way too long. Is that from simulation or actual scope capture?

Haven't seen the schematic of the circuit you guys are talking about, but I'm hearing 1.2Kohm pull-up, 600ohm pull-down, and 100ohm gate resistor. These figures are excessive!!! How much dead-time are you running with? what kind of efficiency are you getting? what about THD? Typically the rise/fall time for a 500KHz switcher is <50ns, and more like 25ns...

Driver pull-down strength should be <3ohm. If it's too weak, to cut the story short, the weak pull-down can't keep the FET off when the switched node is slewing. Pull-up strength is a compromise of EMI and effienciency (and THD in class-D amps). No gate resistor should be needed; if you have ringing/EMI, that means you have layout problems. You may try to limit the pull-up strength somehow, but only without introducing additional impedance in series with the gate. The FET's parasitic gate resistance (>1ohm) and inductance (1nH) is already bad enough you don't need to add more.

That said, you should not be using anything bigger than SO-8 FETs. Okay, DPAK is absolutely the limit. The inductance in those TO-220 packages prevents any switching at serious speed. If you try, at best it runs hot, typically it will run for a second and the package will smoke or explode in your face (depending on the up-stream power supply).

Yes it is from simulation, I know..... I know, not very realistic, poor modeling of parts etc, but I feel it does "demonstrate" the points in question. The model is the pspice advanced analysis IRF540.

You would have seen the circuit had I posted it in the thread I thought I was posting to :(

Dead time? None! This is why such a slow turn on is required, when you look at those gate signals, you're looking at the dead time. Typically when you have a ~25ns rise, you also have a ~200ns dead time. Also excessive. The mosfets themselves still switch very fast, nothing like the gate signals show. You see the little glitch on the gate drive signals caused by the slew of the switching? The mosfet is fully switched in this time.

The 600 ohm turn off is not with respect to driver output impedance, but merely the bias of the turn off transistor, which is your typical PNP speed up active pull down device. The bias of the turn on/turn off active components fight each other in a balancing act which controls how loaded the driver is and when it switches from high to low.

100 ohm in series with the gate isn't so unusual from what I've seen, 50 ohms is commonly used. It does help to decouple wiring inductance from the gate capacitance to avoid oscillations at the gate, also to slow turn on.. This is very often seen in power switching driver app notes and ... everywhere I've seen really.

It might be a stretch to say you have layout problems if you have ringing. Two techniques I know of which dont' use a gate resistor :use trace inductance to form a resonant circuit with the gate, (IXYS app notes, 5Mhz class D, soft switched I think?) this isn't a requirement for the speeds in question, and they don't work with the common DIYr's prototyping techniques.

A constant current driver is another method used to control gate step, and for this method a turn on resistor may not be needed either.

This turn on resistor in question is only in the charge path, and not the discharge path.

Otherwise,
Turn on resistors of 50 to 100 ohms are commonly used. I admit 100 is more rare to see and on the high side, but in this simulation it is the difference between cross conduction and no cross conduction. If I built this I would start with 100 and see how much lower I can take it.

Once again this driver is only optimal in low part count. I would prefer to switch much faster, and use adaptive delay as a solution to much of this. I'll keep researching methods for achieving that.

PS:

I know there's better mosfets to use but the IRF540 is my "standard" for simulation, and it's also worst case since in reality I'd use a better mosfet.

Excellent post, and welcome to the forums. I don't like hot toasted mosfets either.
 
There is no practical device safety limit that prevents using very fast turn off drive (EMI is always a concern, of course), but one must limit turn-on drive in order to observe the (other) device's reapplied dv/dt rating and avoid secondary breakdown of the other device's body diode (the conditions for this typically occur only if the body diode has just been conducting and then is immediately required to support more than about half the device's rated voltage).
 
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ssanmor said:
mmmm, workhorse, your design resembles a lot to what I posted in this forum about 1 year ago or more (LM6172 triangle generator, XOR gates at IR2110 input, LM319 comparator...

I did some experimentation and also with symmetric supplies and no level shift, with all (triangle gen, error opamp and comparator) using a single supply referenced to Vss, with of course capacitive coupling at the input, but had variable offset problems and distortion figures were not very good so I abandoned that approach although it was much simpler.

If that's an experiment and you are doing it to learn and for personal use, no problem for me (that's what this forum was created for).

Have luck.

Hi Sergio
Glad to see you too!
My design was influenced from Crest LT schematic and the triangle generator was from your circuit.
This was only for experimenting with class-D amps , nothing else.

Since Charles had helped us alot in this forum, we are going to improve this circuit with his advise.

But our commercial production will be our own creation no copying at all.

regards,
kanwar
 
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