All,
I'm starting a design of a PowerDAC, I mean a digital input to classe D amplifier.
Some of the solutions are already defined, up to PWM generation at least.
On-going study is driver bridge and bridge at 1 MHz
Parralel study is switched PSU with voltage control.
Aim to publish here : give you my ideas, give me your ones !
Fabien
I'm starting a design of a PowerDAC, I mean a digital input to classe D amplifier.
Some of the solutions are already defined, up to PWM generation at least.
On-going study is driver bridge and bridge at 1 MHz
Parralel study is switched PSU with voltage control.
Aim to publish here : give you my ideas, give me your ones !
Fabien
Your idea has been explored a fair bit... apart from the 1MHz part.
All the TI chipsets do 384kHz and I never investingated the others. I don't think there is a way to 'oversample' the PWM output to 1MHz.
Also, a 1MHz switching stage would probably have very little power ability due to the gate charge on the larger mosfets. Unless you have a very exotic mosfet driver
All the TI chipsets do 384kHz and I never investingated the others. I don't think there is a way to 'oversample' the PWM output to 1MHz.
Also, a 1MHz switching stage would probably have very little power ability due to the gate charge on the larger mosfets. Unless you have a very exotic mosfet driver
I saw some projects with this idea, you're right. And I know it exists some commercial products, like Tact, etc...
A most of DIY projects seem to be still under study, some others without follow-up...
May be this project will only be another one, but anyway, I do not plan to make a revolution in audio world.
Actually, some people made study on PWM frequency according to sound quality. And the result is, to achieve something good to hear, 1 Mhz, at least, is the right frequency.
Again, TI chipsets have this known frequency limitation, that's why I will use a Zetex solution, which is able to deliver 1 MHz PWM frequency.
First simulations show IRF drivers are not good enough, but Intersil has good driver, with better drive and timing capability than IRF ones.
The game is not over, discret solutions is still under mind.
And again, PWM frequency is not the most important point. Min pulse width is the one to be considered.
With a modulation factor of 0.85, min pulse width has to be 75 ns.
Even if this will limit the maximum power available, it may make a more realistic approach.
Simulation let's think this can be achievable with ST MOSFET and Intersil solution.
To clarify, I'm not reproducing the DAX story and I do not announce any revolutionary product.
I just present my work, step by step. So, be free to say what you want on my project, I will still populate my post
Fabien
Hi Fabien,
I would suggest that you first actually take the Intersil or National driver with planned MOSFETS, run them at 1MHz from lab pulse generator and see what you came up with. You might be stisfied, you might be not. I tried it some years ago and was not.
If you want high frequency, I think multiphase approach with autotransformer phase summing (Bruno`s patent) is your best bet.
Best regards,
Jaka Racman
I would suggest that you first actually take the Intersil or National driver with planned MOSFETS, run them at 1MHz from lab pulse generator and see what you came up with. You might be stisfied, you might be not. I tried it some years ago and was not.
If you want high frequency, I think multiphase approach with autotransformer phase summing (Bruno`s patent) is your best bet.
Best regards,
Jaka Racman
Hi Fabian,
The Zetex ZXCW was originally never intended to be used as a standalone digital modulator; there are some undefined modes which format the 8 data lines for an output stage driver chip which would have included local feedback. At the last moment, I suggested adding the direct PWM outputs for low power 10W type applications such as flat panel displays etc, however the modulation strategy in this mode is non optimal – but OK for the intended Mid-Fi 10W flat panel market sector.
The high PWM rate was chosen to avoid EMC issues within the AM band, output stage feedback would then have remove the extra errors caused by the poorer output stage performance at this elevated frequency.
As typical with many project developments - goals where change by the greater powers to be, and the output stage driver was dropped, leaving the direct 1MHz / 2MHz PWM now the only area of development. Left in a totally futile position to design non FB HIGH power, Hi performance output stages at 1MHz+ with a totally non optimal modulation strategy, and the powers to be choosing not to heed my words, I became totally disillusioned - conceded defeat and got out from the project the moment I realised I could no longer add any positive benefit.
Before the design-in of any new modulator, I always audition the modulator in an optimal environment – with a perfect output stage and clock. This basically means adding D-type Latches - clocked with an ultra low phase noise clock to the PWM outputs – integrating this “perfect PWM” and then feeding this line level signal to a reference analogue amplifier. This allows auditioning of the digital filter / modulator in its best form, real life operation will only be worst with poorer clocks and output stages errors etc.
Some may rightly question the benefit of this method, but I believe that if a modulator does not sound good in a "perfect environment" – then its sure as hell is not going to sound good in the real world.
To cut my rumbling short – the ZXCW is the worst sounding modulator I’ve every heard / tested todate – I could be accused of “sour grapes”; however all who have heard my demonstrations support my findings.
The TI5015 ranks as one of the best – if not THE best sounding PWM modulator currently available (I’ve FPGA prototypes and first silicon devices under NDA that sound better) – forget any misgivings about the 384KHz operation – the Zetex in both 1MHz and 2MHz simply cannot compete – and quote from people who have listen – the difference is SIMPLY HUGE (with arms wide apart) – forget any subtleties!
John
The Zetex ZXCW was originally never intended to be used as a standalone digital modulator; there are some undefined modes which format the 8 data lines for an output stage driver chip which would have included local feedback. At the last moment, I suggested adding the direct PWM outputs for low power 10W type applications such as flat panel displays etc, however the modulation strategy in this mode is non optimal – but OK for the intended Mid-Fi 10W flat panel market sector.
The high PWM rate was chosen to avoid EMC issues within the AM band, output stage feedback would then have remove the extra errors caused by the poorer output stage performance at this elevated frequency.
As typical with many project developments - goals where change by the greater powers to be, and the output stage driver was dropped, leaving the direct 1MHz / 2MHz PWM now the only area of development. Left in a totally futile position to design non FB HIGH power, Hi performance output stages at 1MHz+ with a totally non optimal modulation strategy, and the powers to be choosing not to heed my words, I became totally disillusioned - conceded defeat and got out from the project the moment I realised I could no longer add any positive benefit.
Before the design-in of any new modulator, I always audition the modulator in an optimal environment – with a perfect output stage and clock. This basically means adding D-type Latches - clocked with an ultra low phase noise clock to the PWM outputs – integrating this “perfect PWM” and then feeding this line level signal to a reference analogue amplifier. This allows auditioning of the digital filter / modulator in its best form, real life operation will only be worst with poorer clocks and output stages errors etc.
Some may rightly question the benefit of this method, but I believe that if a modulator does not sound good in a "perfect environment" – then its sure as hell is not going to sound good in the real world.
To cut my rumbling short – the ZXCW is the worst sounding modulator I’ve every heard / tested todate – I could be accused of “sour grapes”; however all who have heard my demonstrations support my findings.
The TI5015 ranks as one of the best – if not THE best sounding PWM modulator currently available (I’ve FPGA prototypes and first silicon devices under NDA that sound better) – forget any misgivings about the 384KHz operation – the Zetex in both 1MHz and 2MHz simply cannot compete – and quote from people who have listen – the difference is SIMPLY HUGE (with arms wide apart) – forget any subtleties!
John
Hi John,
Your feedback is exactly what I'm looking for.
Actually, like you understood, my project is in investigation phase. And I'm not so confident in the Zetex solution, at least because the documentation about the modulator behaviour and PWM outputs are very poor.
I intentionally planed to use TI solutions, but because TAS5015 production is ramp-downed, I considerer TAS5118, but in stereo application, not 5.1.
Designing a FPGA prototype is out of the scope of my project, because even if I'm VHDL friendly, I do not want to enter is this consideration.
So, to recenter the project, the idea is the following :
- Define the best ( or considered as ) integrated PWM modulator
- Design a PWM output stage as best as possible
- Design and use PSU modulation to improve accuracy and dynamic.
Actually, dynamic voltage scaling feature is integrated is TAS5118, but external solution may be used in all cases.
A question : I read and read again classD amplifiers are not a digital design, and I agree.
But with digital PWM modulator, the pulse varies in a discrete way. So, can't we consider, in that case, that it is a digital approach ?
Fabien
Your feedback is exactly what I'm looking for.
Actually, like you understood, my project is in investigation phase. And I'm not so confident in the Zetex solution, at least because the documentation about the modulator behaviour and PWM outputs are very poor.
I intentionally planed to use TI solutions, but because TAS5015 production is ramp-downed, I considerer TAS5118, but in stereo application, not 5.1.
Designing a FPGA prototype is out of the scope of my project, because even if I'm VHDL friendly, I do not want to enter is this consideration.
So, to recenter the project, the idea is the following :
- Define the best ( or considered as ) integrated PWM modulator
- Design a PWM output stage as best as possible
- Design and use PSU modulation to improve accuracy and dynamic.
Actually, dynamic voltage scaling feature is integrated is TAS5118, but external solution may be used in all cases.
A question : I read and read again classD amplifiers are not a digital design, and I agree.
But with digital PWM modulator, the pulse varies in a discrete way. So, can't we consider, in that case, that it is a digital approach ?
Fabien
Pcm - Pwm
Fabien:
Popping from the other thread (Good audio PWM IC's) as per your advise, here are links to very good papers by Pascual, Sarwate et. al.
Complete digital audio inverter and background (with some overlap)
Hope it helps; Rodolfo
Fabien:
Popping from the other thread (Good audio PWM IC's) as per your advise, here are links to very good papers by Pascual, Sarwate et. al.
Complete digital audio inverter and background (with some overlap)
Hope it helps; Rodolfo
Rodolfo,
These articles are very interesting.
As a first synthesis :
- non multiphase systems still have a good potential
- algorithm is critical, but we already know that
- differential study between natural and uniform PWM shows clearly what has to be selected
- Noise shaping section has to be carefully designed
Moreover, it opens the door for digital controlled switch time of FET drivers.
And shows clearly closed-loop may be implemented in digital PWM design, with sucess
Thanks again because it's completly changed my first approach and it improved my understanding.
Not so many thanks ( ) because right now, I now I have to design and implement my own algorithm !
So let's start a TI DSP selection and write some piece of code...
Fabien
These articles are very interesting.
As a first synthesis :
- non multiphase systems still have a good potential
- algorithm is critical, but we already know that
- differential study between natural and uniform PWM shows clearly what has to be selected
- Noise shaping section has to be carefully designed
Moreover, it opens the door for digital controlled switch time of FET drivers.
And shows clearly closed-loop may be implemented in digital PWM design, with sucess
Thanks again because it's completly changed my first approach and it improved my understanding.
Not so many thanks (
) because right now, I now I have to design and implement my own algorithm !So let's start a TI DSP selection and write some piece of code...
Fabien
Any people which has an interrest in digital class D will conclude than loopback is the key point.
Actually, here is the same case for analog class D.
For fun, I saw on internet an IEEE article written by Bruno Putzeys saying the same
So, because I'm working on a class D digital design, for my personnal use and technical skill improvment, I decided to add a loopback in my original design.
Some existing articles confirm again than a good approach may be to use an adaptive filter, due to the delay introduced by the PCM to PWM chain and the delay introduced bu the A/N loopback chain.
Does anybody already try to work in that direction and does anyone has a ... feedback ?
Fabien
Actually, here is the same case for analog class D.
For fun, I saw on internet an IEEE article written by Bruno Putzeys saying the same
So, because I'm working on a class D digital design, for my personnal use and technical skill improvment, I decided to add a loopback in my original design.
Some existing articles confirm again than a good approach may be to use an adaptive filter, due to the delay introduced by the PCM to PWM chain and the delay introduced bu the A/N loopback chain.
Does anybody already try to work in that direction and does anyone has a ... feedback ?
Fabien
Hi Jaka,
Thanks a lot for the link and PEDEC naming.
This approach in very interresting but it has been patented, so even if I reuse it for myself only, I will be unsatisfactory by this fact. May be I will try it, to see if performances are really here.
I guess yes in fact !
But I'm trying to work in a different approach, i.e. using an complete digital loopback, between the load and the modulator, through AN conversion.
The idea, not mine : found in an article in the web, is to use an adaptive filter in the feedback loop, associated with an image of the input delayed by, at least, the sum of the global modulator delay plus AN converter delay.
Designing such a kind of filter is quite challenging, but that's why I have an interrested to do it
For sure, the goal is to improve PSRR, non-linearity of power stage and load variation.
If you have any feedback, according to your own analysis, they are welcome.
At least, do you think it does make sense to work on this algorithm ?
Fabien
Thanks a lot for the link and PEDEC naming.
This approach in very interresting but it has been patented, so even if I reuse it for myself only, I will be unsatisfactory by this fact. May be I will try it, to see if performances are really here.
I guess yes in fact !
But I'm trying to work in a different approach, i.e. using an complete digital loopback, between the load and the modulator, through AN conversion.
The idea, not mine : found in an article in the web, is to use an adaptive filter in the feedback loop, associated with an image of the input delayed by, at least, the sum of the global modulator delay plus AN converter delay.
Designing such a kind of filter is quite challenging, but that's why I have an interrested to do it
For sure, the goal is to improve PSRR, non-linearity of power stage and load variation.
If you have any feedback, according to your own analysis, they are welcome.
At least, do you think it does make sense to work on this algorithm ?
Fabien
SudFab said:
Have you analyzed this idea in depth?
I mention it for I was thinking on similar lines and have the purpose to explore it in the near future, but am not quite sure the effects of this so introduced pole has in stability.
I currently believe (not working at it yet) that a predictive strategy could be inherently more stable though less accurate, but this is only speculation on my part right now.
Rodolfo
It meets my first idea, but to be honnest, I didn't already perform a real depth analysis.
I'm working on a model which includes perturbation sources, like power supply variation, loud speaker model and power stage distorsion.
After that, I have to look for the better adaptive algorithm and implementation and next run some Mathlab simulations.
Because I do it during my free time, I prefer to not give a target date to publish my first results
Some papers on web let's suppose a amelioration by a factor of 10 on the full bandwidth THD at nominal power, versus open-loop architecture...
Fabien
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