First, the disclaimer... I'm only a 4th year EE student doing this for our design project course, so I'm pretty lacking in experience with this branch of electronics compared to lots of you (I assume).
We're looking at using the IRF530NS or IRF23N15D for output mosfets in a non-H bridge configuration, 100W class D amp. For gate drivers we're looking at the IR2011
Our curriculum doesn't so much as mention gate drivers, and I've found almost no info about their basic function, except for the little bit of info in part datasheets. I gather they're used to introduce a dead time to prevent both mosfets from conducting simultaneously (thereby reducing efficiency). I've obtained spice models for both the drivers and the mosfets, but I'm really fuzzy on what "low side supply" versus "low side return" are etc etc. Nor do I understand the functional block diagram in the IR2011 datasheet.
If anyone can point me in the right direction, tell me where to start looking, or even give a comprehensive explanation, I'd really appreciate it. Thanks,
Dave, I'm about in the same boat. I am planning to use the IR2011S in a 150W into 4ohm Class D amp for my senior project as well. However, I have some industry experience with a Class D amp using the IR2010 gate driver. Here is what I can tell you:
The gates of the FETs have to turn on and off at certain times. As you said, the gate driver makes this happen at the correct time. It also provides high current outputs to drive the capacitance of the FET gates and make the turn on/off happen quick. Finally, it provides the power to pull the upper gate 'up' to turn it on. This is known as bootstrapping. A cap is charged above V+, then when the upper FET turns on, that cap cap holds the gate on until it is time for that FET to go off. Then the cap charges so it will be ready to hold the upper FET on at the next switching cycle. That's the majority of it I believe. The propogation delays are also matched in the IR gate drivers so that switching happens much closer to the time when it should, which greatly reduces losses.
I agree that the IR datasheet is rather cryptic. I was planning on using the SG3525 to drive the gate driver, and I know, but I am having trouble figuring out how to hook them up together. From the SG3525 datasheet, it seems like the pulses aren't correct to turn on the FETs correctly. I don't know. Any of you geniuses out there care to help enlighten us? :)
Yeah, don't be too shocked if those spice models aren't worth a damn.
In fact, be shocked if they do work at all.
First the disclaimer, I have some canadian education as well.
Now then, I believe I can introduce you to a few basics about it.
Some drivers are only good for Vcom=ground, in which case your signal ground will have to be split between ground and the positive power rail in order for the output to be symetrical. This obviously isn't the best way because your output always has a fair bit of DC on it with respect to earth ground. This is how it appears on the data sheet.
All voltages on the data sheet are referenced to this common point. I see no reason why you can't make this comming point a negative power rail, provided you level shift the inputs accordingly, if the sheet say's max input voltage is TTL level, this TTL must be then be referenced to the negative rail. It's extra hasle, though it saves you having to reference your output signal common point to being split between earth and the positive rail, as output signal common then becomes earth common, safer.
So let's say you had +-30Vdc power rails, then both Vin signals would have to be level shifted down to -30Vdc, so that it transitions between -30Vdc and -25Vdc to turn it on.
Vcc could be 15Vdc, , also referenced to the -30Vdc rail, so then it's actually -15Vdc with respect to earth.
As explained Vs is for the bootstrap circuit. In order for the high side switch to turn on (N channel) it has to be pumped up Vdrive (15Vdc in my example) above the positive power rail, referenced to the source of the of the high side switch (Vsource), which is also your half bridge's output node.
I recommend two things:
Start hitting some application notes, all you can find regarding gate drives, driving mosfets, etc. IXYS, Fairchild, IR, and TI have some good ones. This isn't a simple thing to get working well, and they won't answer all your questions or solve all your problems, but you'll be better off for having done it.
Second, to learn about level shifting and logic interfacing, seriously, get a copy of "Art of Electronics", excellent book.
Might want to do some searching on minimising loop inductance in gate drivers.
Even app notes that have little to do with your application can give you some great tips (like RF or resonant switching).
Hope that helps, good luck.
for starters, read AN978 .
The gate drivers you are referring to will not introduce dead time
to prevent overlap. This will be done in the controller circuit.
The drivers are just made to drive the gates with as little influence
as possible regarding timing. That is why the hi / lo sides are matched
Came across this page while looking for pcb layout tips
The third link is quite interesting
I do have a schematic using the IR2111. Let me know if you are interested.
I'd like to see it
I'd also like to see any PCB layouts that anyone has just to get an idea of how to route power to a full bridge while keeping all the fets in a straight line - maybe I should start a new thread for that
here it is...
Isn't this from the JBL sub woofer amp that you and many others have had trouble with ?
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