Output devices?

Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.
As an initial foray into class-D, I've been doing some simulations of a very simple circuit consisting of a triangle wave generator, a comparator and a couple of MOSFETS (surprisingly good simulation results from a circuit with only a handful of components in it).

The output stage is one N and one P-channel MOSFET - the simplest arrangement possible. The problem is finding a suitable pair of complementary devices. Ones sold for linear use often have their complements clearly marked. Ones for switching either don't have complements or it's not obvious what they are.

So what would make good output devices for various power levels? Perhaps it would be easier to use a bridge driver and use only N-channel MOSFETs?

And on a related note: Could IGBTs be used? How would they compare to MOSFETs?
 
Hi,

Using a P channel is a compromise, in order to be able to use simpler gate drivers.

You only get one advantage by using a P channel and that's ... the easier drive circuit. That one advantage costs you alot, mismatched capacitances, greater body diode drop, slower overall, higher Ron..

There's a number of reasons for all this but the main thing is they use holes as charge carriers, which is less efficient than N channel FETs, which use electrons.

I've seen some go for a much larger P channel in order to match Ron, and all other things be damned.

Ideally, you really want to use two N channels, only way for it to be truly symmetrical.

There's a good choice of high end drivers out there that will allow you to do it easily enough (non you can actually simulate with as far as I know), and if you look at the UCD circuits around here you'll see a discrete method which should provide some good insight as to how it's done discretely, and which do simulate easily enough.

Cheers,
Chris
 
Hi 666,

I use the following devices for power levels to 120W 8 Ohms, the Siliconix devices being the best switchers - but the Fairchilds are very good. Devices are SMD, and require no heatsinking for the above Cont. power levels.

SUD15N06 / SUD10P06 Siliconix
Si7414DN / Si7415DN Siliconix

FDD5612, FDD5614 Fairchild

If anyones interrested I can post OPS circuits.

John
 
Clicked the wrong link..

Here's the schematic
 

Attachments

  • driver.gif
    driver.gif
    6.3 KB · Views: 756
Hi Chris,

As a recommendation, move R47 to the first EF pair – this will allow the second pair to offer a lower impedance to the Reverse Miller Charge. To this end, Q80 need only be a cheaper BC something…

Due to the EF voltage drops – you will probably need to Capacitor couple the Gate Drive, and return the Gate to nearer 0 volts. As FETs heat up, Vth reduces…

Will post circuits when I dig them up…
 
Hi John,

Would you only change q80 and leave q81 as is, just to add the "soft" dead time etc. Or change them both? I know keeping them all matched doesn't really matter but it's something I have to talk myself into :) Though, I had tried that many many posts ago and it simulated exceptionally well.

I love the idea of 0Vgs ability but.. the only way I can think of actually making capacitive coupling work envolves adding another resistor from gate to source, after the cap, otherwise gate voltage is no longer with respect to source. Then we have higher impedance seen by the miller charge again. Is there another way to do it?

I've seen other ways of generating even negative gate drive, type of charge pump, might look into that but I'm not sure how good it would be.


Regards
 
The “killer” in switching Fets is Toff Delay. Ideally, you want as low pull-down impendence (fast) as you can (Toff), and have a “Soft” rising edge (Ton Gate drive) – but the reverse miller charge is also a problem – so the best solution is to have slower but low impedance rising edge, and a fast and low impedance as possible falling edge. That’s why its better to have the “soft” rise-time resistor in the proceeding EF pair – to a degree, the final stage EF’s provide a low impedance – slower rising edge and “buffer” the reverse Miller charge.

Inserting the resistor in the Emitter “unbalances” the circuit, so you might as well just us a lower current / gain device anyway.

Yes, you need to DC restore the Gate drive signal after AC coupling (Schottky & resistor), but the impedance of the Gate drive will not be adversely effected by the insertion of the capacitor – provided it has good RF qualities – I use “reverse format” types – 0612.

Another method to DC restore is to add a Zener diode across the coupling cap.

John
 
Attached is a REAL simple “budget” 120W 8Ohm OPS in full bridge – it’s designed for “Home Cinema in a box type systems” – but THD is below 0.1%, and still manages to meet thermal requirements using SMD devices and just the PCB as heatsinking (although 4 Layers).

Its crude – but works better and provides higher power (cheaper) into 8 Ohms than “Integrated” OPS designs I've tried.

Note that the driver stage PSU rails are also AC coupled to the HBridge supplies to provide a low impedance Toff path between the Gate & Source of each FET and the Driver circuit.

The choice of “level” shift device (the Si1539), doesn’t have the lowest RDSon in the range – but can be switched fast with a single logic gate, without excessive cross-conduction.

Notice the “funky” :) crossed coupled Soft dead time circuit….

This circuit only works well with the SUD devices - which are very fast, I tried the Fairchild FDD5612 / 5614, but the Pch Toff delay is to long, resulting in an Iq of about 50mA per Half bridge :(
 

Attachments

  • budget 100w ops rev 1.pdf
    30.4 KB · Views: 302
“Ton” switching of the above circuit, slow – but no ringing – notice the “attack” by the reverse Miller charge as Gate reaches Vth – Hey common guys it’s a simple circuit – have any better / cheaper :)
 

Attachments

  • budget ops ton v1.jpg
    budget ops ton v1.jpg
    24.7 KB · Views: 608
The first circuit “Real Simple OPS” full bridge,

And the second, a 250W+ 4Ohm OPS using leadless devices (in full bridge - not shown).

Note the Hard Deadtime resistors (R9 / R4) and the Soft Deadtime resistors (47R & 33R) should only be taken as guide values – as I don’t believe I updated the circuit diagram after “optimising” the circuit on the bench.

Also, a small drawing error, there should be 100pF capacitors to ground on the inputs to each NC7WZ04P6 - (so that’s 2 extra Caps to ground).

The above OPS is VERY fast, low distortion, and can provide incredible output power levels for output devices less then 3mm Sq – with no heat sinking!

John
 

Attachments

  • simple bridge & fast ops.pdf
    48.1 KB · Views: 305
Hi Chris,

The 47K resistor function is only to keep the Gate "OFF" with no drive signal – DC restoration is performed by the Schottky diode. The reverse miller charge is an AC phenomenon, which is held into check by the low impedance return path to the driver stage.

Looking at the Pch device, the reverse Miller charge is coupled back into the driver stage via THREE capacitors! The first, the Gate capacitor, then the cap from HBridge to Positive driver supply, then lastly the Cap. from the Positive driver supply to Ground!

Where there is significant Miller Charge (such as with the Si7414DN), I couple the EF’s supply decoupling capacitor directly to the Source of the Output FET via 2 capacitors to allow the lowest impedance path in BOTH directions. One capacitor path for the Reverse Miller charge (connected to EF pair’s Ground connection), and the second to allow rapid Toff discharge (to the EF pair’s Positive supply). Decoupling capacitors are connected directly across the supply rails to the EF pair’s, level shift Fets & 04 inverters – which are not shown on the circuit diagrams for clarity.

I tend to always see a greater reverse Miller charge “spike” with the Nch devices, I believe this is due to there Lower Gate resistance (about 2.5 to 3 times lower then Pch devices). In the Pch devices, I believe their higher internal Gate resistance dissipates some of the “Spikes” energy – but this is only a “John’s - back of the mind theory”… However, the truth may lay somewhere else!

John
 
Also, if so, would it hold true for even higher rails?

I don't recommend using Pch/Nch OPS above +/-27V due to the lack of Fast swtching Pch devices above 60V (this limits the power to about 140W Max 8ohms - full bridge).

Also the Pch RdsOn becomes an issue at higher power levels. The above Si7414/15 is good for 140W 8Ohms with no heatsink - just PCB mounted (about +45 Deg C above ambt. after 30 Min. at rated FULL power). Remember these OPS devices are JUST 3mm Sq!

Indeed, working with it these everyday, I tend to forget how good these OPS devices really are!

This is not a DC power supply, so with Real music the devices don't even appear to heat up! With the very fast switching, and correct Deadtime, switching losses are very low at 384KHz.

John
 
Hello John, Chris, and all,
Well, I guess I will mention the idea I have been studying and doing some experiments with, seeing how John has introduced the use of SMD MOSFETs as outputs in a class D amplifier. Congratulations, JohnW.

I have built a test SMPS circuit using the fast switching IRF7492 SO-8 devices instead of full-sized MOSFETs. The results so far look good.

For an amplifier, I am considering using the IRF7490 operating on 45v rails. I would parallel at least two devices per supply rail for switching power to the speaker. The circuit may use an extra buffer after each usual MOSFET driver to reduce switching times. No heatsinks are involved like in JohnW's approach.

see IRF parametric table. Go to Discrete HEXFET Power Mosfet. Then check Package: SO-8, Polarity: N,
VBRdss: 100 - 300.

As some folks may recall, I suggested the notion of stacking components to eliminate circuit paths. That idea works well with the SO-8 devices. I would plan on the amplifier to have a bridged output (BTL = bridge tied load). The output power may be able to exceed 500w rms.

The eventual goal of big power from a small size may be attainable once class D switching frequencies break the 5mhz mark, since inductors can be smaller then. One limiting factor in downsizing and speeding up is the high frequency characteristics of (bypassing) capacitors. Bruno kindly brought up this problem in another thread.

Admittedly, since efficiency is of primary importance to me, I actually use only the highest frequency which requires virtually no heat sinking. This way switching losses are lessened.
 
subwo1 said:
The eventual goal of big power from a small size may be attainable once class D switching frequencies break the 5mhz mark, since inductors can be smaller then. One limiting factor in downsizing and speeding up is the high frequency characteristics of (bypassing) capacitors. Bruno kindly brought up this problem in another thread.

Admittedly, since efficiency is of primary importance to me, I actually use only the highest frequency which requires virtually no heat sinking. This way switching losses are lessened.
Please be advised that mosfets subjected to too high a reapplied dv/dt may fail catastrophically. Not all mosfets are characterized for this parameter. Those that are, are typically rated for a dv/dt of few volts per nanosecond to a few tens of volts per nanosecond. Several years ago I attempted to use some Motorola devices that were unrated in this regard and found that they failed at dv/dt rates several orders of magnitude slower than this. Even though the data sheets looked as good or better than that of the IR part I wanted to replace, the Motorola parts were completely unsuitable for class d applications. (Since then, I think they have greatly improved their mosfet processing.)

The problem occurs when a mosfet is conducting moderate to substantial current in the reverse direction and is then called upon to support voltage in the forward direction. The reapplied dv/dt rating apparently goes down with temperature and with the magnitude of reapplied voltage (one manufacturer advised me that dv/dt would not be a concern if the parts were never used at more than 40 percent of their voltage rating).

In practical terms this dv/dt limit means that, in a totem pole configuration, there is a limit to how fast a mosfet may be turned on (but not turned off).

Regards -- analog(spiceman) :headshot:
 
analogspiceman said:


The problem occurs when a mosfet is conducting moderate to substantial current in the reverse direction and is then called upon to support voltage in the forward direction. The reapplied dv/dt rating apparently goes down with temperature and with the magnitude of reapplied voltage (one manufacturer advised me that dv/dt would not be a concern if the parts were never used at more than 40 percent of their voltage rating).

In practical terms this dv/dt limit means that, in a totem pole configuration, there is a limit to how fast a mosfet may be turned on (but not turned off).

Regards -- analog(spiceman) :headshot:

:) I am glad you added those caveats. I was thinking in terms of the rated rise and fall times as well as the turn-on and turn-off delays.

I make gate turn-off circuits have quite a bit more drive capability than turn-on ones so didn't think of the diode recovery problem. At least as the totem pole supply voltage is reduced, the Miller effect becomes less of a problem since the ratio of Vds to Vgs(th) goes down.

Technology has quite a way to go before high switching frequencies are practical. One help may be to place a 3 or 5 ampere Schottky diode parallel to the SO-8 MOSFET body diodes. Indeed body diode recovery is very important to consider.
 
Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.