UCD180 questions

[Joseph K]

Hm. In the meantime I had made the transition into "autoconvincement" mode.. So, I have to admit, Bruno, you had been right! I should not go, never, by memory..

Maybe it can be still interesting, so I would post the graphs in question..
First, I started with a 470 uF / 100 nF small film cap combo, because the SMD ceramic one kept on braking on me..
The highlighted curve is the resonance peak / dip generated by the 470 uF/63 v // 100nF /63v combo.
The second trace is the same, but there is a small size .22 ohm put in series with the film cap, towards ground.
As it can be seen, both the resonance peak / dip are dampened, the resulting impedance trace is smoother, but there is the obvious loss in decoupling effectiveness towards the high frequency asimptot, not only the loss at around the series resonance dip [which is a small area, as I noted before]. This loss is at around 2 - 3 dB.
Pardon me for the photo quality, the next ones will be better.
Note the resonance peak without damping, it reaches more than 1 ohm. This is the problem, which could cause ringing at switching edges.
The res. peak is at around 3 MHz.

[Bruno Putzeys]

Well even if this particular idea didn't immediately bring any "advancements to the art", seeing someone look at things in this detail is refreshing. Looking forward to further brainwaves from your part!

[Joseph K]

In the next step I was more succesfull in installing a 0806 / 100nF /50 V smd capacitor. So here it is the resonance generated by the 470 uF // 100 nF smd parallel combo. Though the ESR of these two caps is not very much different, because of the much lower stray inductances, the high freq. attenuation effect is better by ~ 10dB. Also the series resonance dip is shifted to a higher frequency.

[Bruno Putzeys]

Yes, but the parallel resonance is the one that's causing trouble. The series inductance which is part of the series resonance shows up as part of parallel LC circuits formed by the Cd of the "off" fet and the inductance of the mosfet leads and to a lesser extent the decoupling cap. Here, the inductance of the cap is clearly negligible. On the other hand, the lower inductance clearly does pay off towards keeping the supply feed clean (requiring the layout to be "4-point").

[Joseph K]

Now I have put the "snubbing", small capacitor in parallel. So here there is the 470 uF // 47 uF // 100nF combo.
The resonance peak is damped, the dip is unchanged, and as a beneficial effect of the new cap's self-inductance paralleling out the original combo's ESL, the high frequency attenuation has dipped by ~ 3-4 dB. Also the resulting ESR is decreased a bit, though not much.
So, as a sum, this variation is really a much better decoupling method, then putting the series resistance.
In my defense I could only note, that as you can see, the resulting impedance / phase curve is, anyway, smoother with the series resistance method. [less ringing?] Maybe a combination of these could work? Note also that the parallel resonance peak had been damped in an equal manner, in both cases. [Though I was using only .22 ohm]

Ciao, George

[Joseph K]

Bruno, thanks for your notices! But you're typing too fast! [for me..]

Ciao, George

[Joseph K]

P.S.>
I just got curious about this last possible combination that I have previously mentioned:
470uF // 47 uF // 100nF smd +.22 ohm series
Well, it still shows a lot of degradation in the high frequency range - but I will also show You the practical setup, so as to be able to judge: worse than this would be really difficoult.. so what would happen if it were realized on a pcb, with - one - smd resistor?

The highlighted trace is the impedance, the second one is the phase.
You would not want to see the phase plot of the previous graphs...

[Joseph K]

oops, the plot:

[Joseph K]

And the jig [uugghhly..]

[Bruno Putzeys]

Originally posted by Joseph K
so what would happen if it were realized on a pcb, with - one - smd resistor?

Most certainly the HF performance would be better. It's not very hard to try it out in practice. One can lift the 100nF off the PCB and solder it back in series with the smd resistor in a "card-house" fashion. I don't have an EMC test rig here (it's in Groningen, about 350kms north from here), but it's something to try out. If EMI is not significantly affected, the next step is to see if we find an improvement in audio performance.

Originally posted by Joseph K
You would not want to see the phase plot of the previous graphs...

Jumpier as Q's are higher of course.

Originally posted by Joseph K
And the jig [uugghhly..]

Looks like a normal jig for network testing to me