Development of a "reference" class D starting point

[subwo1]

Originally posted by classd4sure


Then I guess neither IXYS' or TI's solutions would be good ....sounds alot like BCA junk.

I'll dig up the diagram of one or two of the pulse transformer implementations I had in mind and post em here just for kicks.

I'm starting to lean away from the idea though.

Those darn opto's....are such a tease aren't they?
I thought of even using a PVI as an overly simple gate drive power source, but they need an off period ..

You can get opto's fast enough, and they're a brilliant idea, but the derating they suffer is disgusting and there's just no way around it.

I would think the short life expectancy would be a big problem if the LED is driven near its maximum current rating. Maybe they have a problem of needing to be driven so hard to function well. But even the 6N137, the fastest most common one I have suffers from a propagation delay of over 100ns IIRC--not a big problem for a high power sub amp though. "There you (I) go again."

[subwo1]

I had a chance to look up the 6N137. The Fairchild datasheet lists a typ. prop delay of 45ns, max 100ns; rise time of 50ns; fall time of 12ns; pulse width distortion of 3ns, max 35ns. The rise time figure seems applicable to a 5 volt supply on the high end of a 350 ohm collector pull-up resistor. For 12v, plan on a 1000 ohm value of such a resistor.

[classd4sure]

Hi there,

My three ways are my subs I've abused them far too long on class A/B..In the end, the speakers won......the amp died.

Here is one very interesting implementation of a large duty pulse transformer, he even prototyped it on a cheapo plastic breadboard, and the real world results look pretty convincing to me, this could be a contender.

http://dsms.ajusd.org/~fritz/AN1.pdf

Fig 11, 14A, 17.
http://www.ixys.com/tmosign2.pdf

Ok.. Had another interesting one but it's vanished.

[phase_accurate]

I'm still uncertain as to how the gate drive signals are biased in your design but I'm sure Charles won't mind filling us in.

Since the input of the two drivers can only swing between -35 and -25 volts approx proper gate-drive is automatically achieved with the drivers using a gain of 1.
I am not sure however if all simulators allow that the output of a voltage controlled voltage source can be referenced to any desired point (isn't that a nice high-side driver ? ).

I didn't even have a close-enough look at the original patent. I just threw together a circuit with a comparator, an output filter and a "lead part" in the feedback. Since I am a fan of inverting designs it turned out inverting.

As to simulation results: Different simulators might simulate differently, so one has to tweak a little. And this counts not only for component values. In PSPICE the simulation parameter RELTOL has great influence. The lower, the more accurate (and usually nicer simulations) but the larger the chance that it can't converge.

BTW: you might have remarked that the gain in my circuit is only somethig below about 5. The circuit simulated nicer with lower (voltage-) gains, that's the reason why I chose it that low.

regards

Charles

[classd4sure]

Hi,

I possibly dont' understand how that source works at all. Seems like an odd place as it looks like it's on the wrong side of the source.

So I guessed right about why you're summing the feedback with the input instead of taking the difference....I impressed myself.

Anyway, I was wondering what the lower threshold of your input sensitivity was, about 100mV is the best I had.

Regards,
Chris

[Bricolo]

Originally posted by classd4sure


Sorry, I'd like to help ya with that but I can't. All I can do is take screenshots with it, if I zoom in enough to see the part values better I'll only be able to get 1/10 the circuit in the screenshot, then I'd have to flood the forum with a bunch of partial circuit badly implemented screenshots ....

you can take a bigger screenshot, zip it, and attach it

you won't be limited by the image size resolution limit

[phase_accurate]

Anyway, I was wondering what the lower threshold of your input sensitivity was, about 100mV is the best I had.

I don't understand what you mean by this.

Regards

Charles

[phase_accurate]

That's how mine simulates. Input signal is about 2 volts. You can see that I also have some offset. I don't think it would be worth to trim around the offset on the simulator. This should be done on a real life circuit. The switching residual is around 1 volt peak. If one wants lower then he has to lower the filter cutoff frequency or increase the switching frequency. Simulated THD is around 0.1 % with k2 dominating and much smaller k3. The rest is way below those two. While the absolute figures aren't that great (I didn't say that it is tweaked for optimum, did I ?), it is basically an optimal THD spectrum.

BTW: This time I used it in non-inverting mode.

Regards

Charles

P.S. if anyone likes to get the .SCH file, drop me a mail.

[JohnW]

In my opinion, it’s almost impossible to design a “correctly” functioning Class D OPS that meets EMC and Audio performance without the use of SMD components.

For best price / performance ratio in the 120W / 8Ohms power range, I find it better to use full bridge topology with Pch & Nch devices for the following reasons: -

Very simple / fast driver stage (but AC coupled – but so is any transformer solution). I would be concerned about guaranteeing start-up and overload “recovery” with any AC coupled solution – the FB integrator requires the correction operation of the overall Feedback-loop to establish its correct DC conditions.

Lower PSU rails say +/- 25V, which allows with care the use of 60V FET’s – with there inherently faster switching times and lower RdsOn.

Symmetrical +/-25V rails allows the use of cheap / high performance (low ESR) 35V electrolytic capacitors. It’s much harder to find good low ESR / low priced electrolytics above 35V.

Allows the use of “cheap” 50V SMD ceramic capacitors for HF decoupling.

Things fail with less “Bang” at lower voltages.

Cancellation of “Even” order distortions (but arguably, sonically this might not be the best thing), & PSU pumping – at 100W single-ended, this is an important issue.

Does not the feedback reduce the effects of PSU pumping? As the PSU rails increase, would not the feedback REDUCE the PWM modulation index to compensate for the INCREASING positive gain error of the OPS? (as the PWM modulation index reduces so will the PSU pumping) I have no experience of “hysteretic” type switchers – what happens to the switching frequency during “Pumping” – I’m guessing it reduces?

A well designed Pch / Nch output stage can switch at 1.5MHz (+/- 70mA quiescent current), with 5nS Hard deadtime and say a total of 25nS OPS propagation delay (maybe not an advantage with hysteresis switchers?).

When I look at my typical OPS designs, which while simple and cheap, use SMD components - which are not easy to source, and require good four layer PCB design skills – none of which meets the DIY constructors requirements.

The best performance 60V MOSFET’s I’ve found and used to date are: -

Vishay – Siliconix’s

SUD10P06-280L
SUD15N06-90L
Si7414DN
Si7415DN

Fairchild

FDD 5612
FDD 5614P

The Vishay – Siliconix’s devices being the best switchers. For good high speed switching Toff Delay and D-G reverse Miller charge are the most important parameters.

John

[phase_accurate]

I would be concerned about guaranteeing start-up and overload “recovery” with any AC coupled solution – the FB integrator requires the correction operation of the overall Feedback-loop to establish its correct DC conditions.

That's not a problem at all if you add a parallel DC path.

Symmetrical +/-25V rails allows the use of cheap / high performance (low ESR) 35V electrolytic capacitors. It’s much harder to find good low ESR / low priced electrolytics above 35V.

According to Bruno it's not a good idea at all to use low ESR caps since they tend to increase ringing instead of reducing it.

Things fail with less “Bang” at lower voltages.

But they do it in a less less interesting way (at least from a spectator's point of view ) !

BTW: I tried to increase NFB by about a factor of five on my posted simulation example and it gave a significant reduction in THD and IMD.

Regards

Charles