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Class D Switching Power Amplifiers and Power D/A conversion

Class D amp with 300v mosfets
Class D amp with 300v mosfets
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Old 6th October 2017, 03:49 PM   #1
ionutgaga is offline ionutgaga
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Default Class D amp with si8244 and 300v mosfets

I have made a stereo class D amplifier, which I intend to feed it with +/- 136v for the 4 ohm output load, Fsw=250khz xtal clock. The feedback is taken after the LC output filter, which consists of a 40uh coil and a 1.5uF capacitor, with a zobbel and a notch at Fsw.

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I used the ipp410n30 mosfet and the si8244 driver. The technical data are attached:
IPP410N30N - Infineon Technologies
https://www.silabs.com/documents/pub...ets/Si824x.pdf

For the test, I used a power supply of +/- 50v with a 200VA transformer.
With ipp410n30, I set the dead time to 45ns and I used a group of 22 ohms in parallel with a diode in the grile of each mosfet. I used a 5 ohm snubber with 660pf for good damping. I finded these values following the same recipe described by Chocoholic in the following threads, but i did not get such good measurements in the hardswitching mode, especially connecting the 4 ohm load to -vcc (if the load is connected to + vcc, the spike does not appear as large):
SystemD_2kW, any interest for an open design?
System_D_MD, Class D is like chocolate
SystemD LiteAmp

I would like some suggestions on this spike.

Otherwise, the amplifier works very well, I will show you a few measurements in the following order:

1-residual at output, Fsw=250khz, some glitch, but it's pretty clean

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2-low side mosfet off, idle

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3-low side mosfet on, idle

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4-low side mosfet on, 4r load connected to +vcc

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5-low side mosfet on, 4r load connected to -vcc

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6-low side mosfet off, 4r load connected to +vcc

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7-low side mosfet off, 4r load connected to -vcc

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8-sine 50hz 4r load

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9-sine 1khz 4r load

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10-sine 10khz (some distorsions) 4r load

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11-sine 10khz before distorsions 4r load

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12-square 1khz 4r load

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13-square 1khz no load

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14-square 10khz 4r load

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15-square 10khz no load

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Last edited by ionutgaga; 7th October 2017 at 01:34 PM.
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Old 6th October 2017, 04:26 PM   #2
ICG is offline ICG  Germany
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Quote:
Originally Posted by ionutgaga View Post
I have made a stereo class D amplifier, which I intend to feed it with +/- 136v for the 4 ohm output load
2x136V and 4 Ohm. What do you want to do with 18kW?
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Old 6th October 2017, 04:29 PM   #3
ionutgaga is offline ionutgaga
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With a 20% power supply sag, more like 1400w in 4 ohms.
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Old 6th October 2017, 04:37 PM   #4
ICG is offline ICG  Germany
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Quote:
Originally Posted by ionutgaga View Post
With a 20% power supply sag, more like 1400w in 4 ohms.
Two rails of 136V give 272V. That is p-p, if you want to calculate with rms, it is 192V. Minus 20% 'sag', still 153V. On 4 Ohm that's still 5852W (with impressive 38A btw).
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Old 6th October 2017, 04:48 PM   #5
ionutgaga is offline ionutgaga
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It must be taken into account that the load is connected between the output and the gnd of power supply, like any other amplifier.
For questions like "how much power do I get with a +/- 136v", please check out other sections of this forum.
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Old 6th October 2017, 05:27 PM   #6
doctormord is offline doctormord  Germany
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Quote:
Originally Posted by ICG View Post
Two rails of 136V give 272V. That is p-p, if you want to calculate with rms, it is 192V. Minus 20% 'sag', still 153V. On 4 Ohm that's still 5852W (with impressive 38A btw).
272Vpp is 96Vrms..

20% sag is -54V at 272Vpp -> 218Vpp == 77Vrms

77V^2/4R = 1482W
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Old 6th October 2017, 07:33 PM   #7
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I think I must have fallen on my head today..
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Old 8th October 2017, 03:56 PM   #8
Eva is offline Eva  Spain
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The FETs and the driver are nice.

The peaks in Vds after diode recovery and at turn off with some current indicate the di/dt used (gate drive) is too fast for this type of PCB.

Critical over-current and over-heating protections seem absent. The gate driver does not implement basic current-limiting/shorted-FET shutdown.

The aim for carrier-residual-free output is cosmetical, but it matches the fixed frequency concept.

The triangle wave modulator has weak behavior at HF, and higher switching loss as there is no oscillation frequency drop at high output power, but it is the solution that works for 2 channels with this type of (single) PCB construction, self oscillating requires better SNR. I hope you remember to sync the 2 channels out of phase by 90 deg for best performance, so that at low volume switching in one channel happens "far" in time from the other.

The overall concept reminds of Powersoft, with the same weaknesses. This is a state-of-the-art pre-SMD amplification concept. For driving passive full range speakers it is OK, but the trend is towards multi-amplification at such a power level. For driving fat LF speaker systems the crest factor is not enough.
See amplifier advertised as 10KW, costing seveal "thousands", with similar 300~400V technology, folding back badly after a few seconds due to overshoot in thermal limiter: YouTube
For driving MF it is optimum, but not so much voltage is needed. Same issue for driving HF, but with high impedance motors in horns requiring CD compensation the slew rate limitation could be an issue, as much as the snubber needed at the output dissipating substantial power (modulator becomes far more suboptimal without it).

Good work.

btw: Powering this with a >=10kg toroid would not be in line with class D principles, although it is useful in the bench. The other field of high voltage switching experimentation is SMPS.
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Last edited by Eva; 8th October 2017 at 04:00 PM.
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Old 8th October 2017, 04:30 PM   #9
ionutgaga is offline ionutgaga
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Eva, thank you for the answer.
Sync is done in antiphase on the 2 channels. Smps is also synchronized at 250khz (125khz in transformer).
Can you show me what I should improve on the timing part? I have tried to increase the resistance value of 22 ohms and add a resistance in series with the diode in the grile of the mosfet, I found that i can limit dv/dt to about 1v / ns with nice loking trapezoidal shape, but in this case I have to increase quite a lot of the dead time.
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Old 8th October 2017, 06:35 PM   #10
Eva is offline Eva  Spain
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"Antiphase" does not solve the problem of mutual interference between channels, which is most relevant at low volume listening. The EMI pulse from the 1st channel to switch will disturb the timing of the other easily if both happen in close time proximity. Having an integrator in feedback loop can easily cause this process to bounce, resulting in not clean noise floor. The 90deg clock displacement, instead of 180deg minimizes this problem. This is achieved doubling oscillator frequency and inserting additional /2 divide, and proper logic to get two 250khz waves with one shifted 90deg.

There is still another potential problem, the EMI pulse from one channel disturbing the own channel and making it switch twice, this problem can only appear at high power (full rails, low impedance load, hot), and will ultimately dictate the minimum value of gate resistors (for no self-interference).

It is not dv/dt but di/dt the limiting factor (magnetic field, as opposed to electric field). To understand how to see di/dt you have to understand inductive voltage drop across source lead of FET during turn on and off. Customizing this voltage drop allows to use reasonable values of gate resistors, so that dv/dt and dead time are not compromised. For optimum turn on a low gate drive supply voltage is recommended, about 10V. For optimum turn off the inductive voltage drop across source lead is slightly higher than Vgs threshold and is already optimum. Some additional inductance in series with gate can produce some transient negative voltage at turn off, speeding it up, but this is way too fast for 2 side thru-hole PCB.

To reduce di/dt just make FET leads longer. Source lead inductance (to FET die) measured 5~6mm away from case is about 7nH for TO-220 (not sandwitched between conductive surfaces). For example 3.5V across 7nH are a di/dt of 500A/us.
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Last edited by Eva; 8th October 2017 at 06:38 PM.
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