Class D amp with si8244 and 300v mosfets
I have made a stereo class D amplifier, which I intend to feed it with +/- 136v for the 4 ohm output load, Fsw=250khz xtal clock. The feedback is taken after the LC output filter, which consists of a 40uh coil and a 1.5uF capacitor, with a zobbel and a notch at Fsw.
I used the ipp410n30 mosfet and the si8244 driver. The technical data are attached:
IPP410N30N - Infineon Technologies
https://www.silabs.com/documents/public/data-sheets/Si824x.pdf
For the test, I used a power supply of +/- 50v with a 200VA transformer.
With ipp410n30, I set the dead time to 45ns and I used a group of 22 ohms in parallel with a diode in the grile of each mosfet. I used a 5 ohm snubber with 660pf for good damping. I finded these values following the same recipe described by Chocoholic in the following threads, but i did not get such good measurements in the hardswitching mode, especially connecting the 4 ohm load to -vcc (if the load is connected to + vcc, the spike does not appear as large):
http://www.diyaudio.com/forums/class-d/224052-systemd_2kw-design-6.html#post3379820
http://www.diyaudio.com/forums/class-d/221498-system_d_md-class-chocolate.html#post3220098
http://www.diyaudio.com/forums/class-d/255046-systemd-liteamp-8.html#post4408076
I would like some suggestions on this spike.
Otherwise, the amplifier works very well, I will show you a few measurements in the following order:
1-residual at output, Fsw=250khz, some glitch, but it's pretty clean
2-low side mosfet off, idle
3-low side mosfet on, idle
4-low side mosfet on, 4r load connected to +vcc
5-low side mosfet on, 4r load connected to -vcc
6-low side mosfet off, 4r load connected to +vcc
7-low side mosfet off, 4r load connected to -vcc
8-sine 50hz 4r load
9-sine 1khz 4r load
10-sine 10khz (some distorsions) 4r load
11-sine 10khz before distorsions 4r load
12-square 1khz 4r load
13-square 1khz no load
14-square 10khz 4r load
15-square 10khz no load
I have made a stereo class D amplifier, which I intend to feed it with +/- 136v for the 4 ohm output load, Fsw=250khz xtal clock. The feedback is taken after the LC output filter, which consists of a 40uh coil and a 1.5uF capacitor, with a zobbel and a notch at Fsw.
An externally hosted image should be here but it was not working when we last tested it.
I used the ipp410n30 mosfet and the si8244 driver. The technical data are attached:
IPP410N30N - Infineon Technologies
https://www.silabs.com/documents/public/data-sheets/Si824x.pdf
For the test, I used a power supply of +/- 50v with a 200VA transformer.
With ipp410n30, I set the dead time to 45ns and I used a group of 22 ohms in parallel with a diode in the grile of each mosfet. I used a 5 ohm snubber with 660pf for good damping. I finded these values following the same recipe described by Chocoholic in the following threads, but i did not get such good measurements in the hardswitching mode, especially connecting the 4 ohm load to -vcc (if the load is connected to + vcc, the spike does not appear as large):
http://www.diyaudio.com/forums/class-d/224052-systemd_2kw-design-6.html#post3379820
http://www.diyaudio.com/forums/class-d/221498-system_d_md-class-chocolate.html#post3220098
http://www.diyaudio.com/forums/class-d/255046-systemd-liteamp-8.html#post4408076
I would like some suggestions on this spike.
Otherwise, the amplifier works very well, I will show you a few measurements in the following order:
1-residual at output, Fsw=250khz, some glitch, but it's pretty clean
An externally hosted image should be here but it was not working when we last tested it.
2-low side mosfet off, idle
An externally hosted image should be here but it was not working when we last tested it.
3-low side mosfet on, idle
An externally hosted image should be here but it was not working when we last tested it.
4-low side mosfet on, 4r load connected to +vcc
An externally hosted image should be here but it was not working when we last tested it.
5-low side mosfet on, 4r load connected to -vcc
An externally hosted image should be here but it was not working when we last tested it.
6-low side mosfet off, 4r load connected to +vcc
An externally hosted image should be here but it was not working when we last tested it.
7-low side mosfet off, 4r load connected to -vcc
An externally hosted image should be here but it was not working when we last tested it.
8-sine 50hz 4r load
An externally hosted image should be here but it was not working when we last tested it.
9-sine 1khz 4r load
An externally hosted image should be here but it was not working when we last tested it.
10-sine 10khz (some distorsions) 4r load
An externally hosted image should be here but it was not working when we last tested it.
11-sine 10khz before distorsions 4r load
An externally hosted image should be here but it was not working when we last tested it.
12-square 1khz 4r load
An externally hosted image should be here but it was not working when we last tested it.
13-square 1khz no load
An externally hosted image should be here but it was not working when we last tested it.
14-square 10khz 4r load
An externally hosted image should be here but it was not working when we last tested it.
15-square 10khz no load
An externally hosted image should be here but it was not working when we last tested it.
Last edited:
Two rails of 136V give 272V. That is p-p, if you want to calculate with rms, it is 192V. Minus 20% 'sag', still 153V. On 4 Ohm that's still 5852W (with impressive 38A btw).
The FETs and the driver are nice.
The peaks in Vds after diode recovery and at turn off with some current indicate the di/dt used (gate drive) is too fast for this type of PCB.
Critical over-current and over-heating protections seem absent. The gate driver does not implement basic current-limiting/shorted-FET shutdown.
The aim for carrier-residual-free output is cosmetical, but it matches the fixed frequency concept.
The triangle wave modulator has weak behavior at HF, and higher switching loss as there is no oscillation frequency drop at high output power, but it is the solution that works for 2 channels with this type of (single) PCB construction, self oscillating requires better SNR. I hope you remember to sync the 2 channels out of phase by 90 deg for best performance, so that at low volume switching in one channel happens "far" in time from the other.
The overall concept reminds of Powersoft, with the same weaknesses. This is a state-of-the-art pre-SMD amplification concept. For driving passive full range speakers it is OK, but the trend is towards multi-amplification at such a power level. For driving fat LF speaker systems the crest factor is not enough.
See amplifier advertised as 10KW, costing seveal "thousands", with similar 300~400V technology, folding back badly after a few seconds due to overshoot in thermal limiter: YouTube
For driving MF it is optimum, but not so much voltage is needed. Same issue for driving HF, but with high impedance motors in horns requiring CD compensation the slew rate limitation could be an issue, as much as the snubber needed at the output dissipating substantial power (modulator becomes far more suboptimal without it).
Good work.
btw: Powering this with a >=10kg toroid would not be in line with class D principles, although it is useful in the bench. The other field of high voltage switching experimentation is SMPS.
The peaks in Vds after diode recovery and at turn off with some current indicate the di/dt used (gate drive) is too fast for this type of PCB.
Critical over-current and over-heating protections seem absent. The gate driver does not implement basic current-limiting/shorted-FET shutdown.
The aim for carrier-residual-free output is cosmetical, but it matches the fixed frequency concept.
The triangle wave modulator has weak behavior at HF, and higher switching loss as there is no oscillation frequency drop at high output power, but it is the solution that works for 2 channels with this type of (single) PCB construction, self oscillating requires better SNR. I hope you remember to sync the 2 channels out of phase by 90 deg for best performance, so that at low volume switching in one channel happens "far" in time from the other.
The overall concept reminds of Powersoft, with the same weaknesses. This is a state-of-the-art pre-SMD amplification concept. For driving passive full range speakers it is OK, but the trend is towards multi-amplification at such a power level. For driving fat LF speaker systems the crest factor is not enough.
See amplifier advertised as 10KW, costing seveal "thousands", with similar 300~400V technology, folding back badly after a few seconds due to overshoot in thermal limiter: YouTube
For driving MF it is optimum, but not so much voltage is needed. Same issue for driving HF, but with high impedance motors in horns requiring CD compensation the slew rate limitation could be an issue, as much as the snubber needed at the output dissipating substantial power (modulator becomes far more suboptimal without it).
Good work.
btw: Powering this with a >=10kg toroid would not be in line with class D principles, although it is useful in the bench. The other field of high voltage switching experimentation is SMPS.
Last edited:
Eva, thank you for the answer.
Sync is done in antiphase on the 2 channels. Smps is also synchronized at 250khz (125khz in transformer).
Can you show me what I should improve on the timing part? I have tried to increase the resistance value of 22 ohms and add a resistance in series with the diode in the grile of the mosfet, I found that i can limit dv/dt to about 1v / ns with nice loking trapezoidal shape, but in this case I have to increase quite a lot of the dead time.
Sync is done in antiphase on the 2 channels. Smps is also synchronized at 250khz (125khz in transformer).
Can you show me what I should improve on the timing part? I have tried to increase the resistance value of 22 ohms and add a resistance in series with the diode in the grile of the mosfet, I found that i can limit dv/dt to about 1v / ns with nice loking trapezoidal shape, but in this case I have to increase quite a lot of the dead time.
"Antiphase" does not solve the problem of mutual interference between channels, which is most relevant at low volume listening. The EMI pulse from the 1st channel to switch will disturb the timing of the other easily if both happen in close time proximity. Having an integrator in feedback loop can easily cause this process to bounce, resulting in not clean noise floor. The 90deg clock displacement, instead of 180deg minimizes this problem. This is achieved doubling oscillator frequency and inserting additional /2 divide, and proper logic to get two 250khz waves with one shifted 90deg.
There is still another potential problem, the EMI pulse from one channel disturbing the own channel and making it switch twice, this problem can only appear at high power (full rails, low impedance load, hot), and will ultimately dictate the minimum value of gate resistors (for no self-interference).
It is not dv/dt but di/dt the limiting factor (magnetic field, as opposed to electric field). To understand how to see di/dt you have to understand inductive voltage drop across source lead of FET during turn on and off. Customizing this voltage drop allows to use reasonable values of gate resistors, so that dv/dt and dead time are not compromised. For optimum turn on a low gate drive supply voltage is recommended, about 10V. For optimum turn off the inductive voltage drop across source lead is slightly higher than Vgs threshold and is already optimum. Some additional inductance in series with gate can produce some transient negative voltage at turn off, speeding it up, but this is way too fast for 2 side thru-hole PCB.
To reduce di/dt just make FET leads longer. Source lead inductance (to FET die) measured 5~6mm away from case is about 7nH for TO-220 (not sandwitched between conductive surfaces). For example 3.5V across 7nH are a di/dt of 500A/us.
There is still another potential problem, the EMI pulse from one channel disturbing the own channel and making it switch twice, this problem can only appear at high power (full rails, low impedance load, hot), and will ultimately dictate the minimum value of gate resistors (for no self-interference).
It is not dv/dt but di/dt the limiting factor (magnetic field, as opposed to electric field). To understand how to see di/dt you have to understand inductive voltage drop across source lead of FET during turn on and off. Customizing this voltage drop allows to use reasonable values of gate resistors, so that dv/dt and dead time are not compromised. For optimum turn on a low gate drive supply voltage is recommended, about 10V. For optimum turn off the inductive voltage drop across source lead is slightly higher than Vgs threshold and is already optimum. Some additional inductance in series with gate can produce some transient negative voltage at turn off, speeding it up, but this is way too fast for 2 side thru-hole PCB.
To reduce di/dt just make FET leads longer. Source lead inductance (to FET die) measured 5~6mm away from case is about 7nH for TO-220 (not sandwitched between conductive surfaces). For example 3.5V across 7nH are a di/dt of 500A/us.
Last edited:
Ionut,
Try ferrite beads over the gate and drain legs, I have achieved very well behaved controlled rate di/dt waveforms with them, especially during reverse recovery in clocked designs.
Your mosfet is not so fast with Reverse recovery time at 152nS and Reverse recovery charge around 844nC which
actually increases at high temperature operation. Though in reality the charge accumulation depends on the time spent during forward path conduction of the body diode and associated parasitics plus rate of allowed di/dt which is higher in your case than the datsheet specs. Hence the flush out or reverse recovery due to short deadtime could be even faster.
Also in my experience, quadrature phased clocks are better option than anti phase clocks, one of the well known brands is doing the same as well.
Try ferrite beads over the gate and drain legs, I have achieved very well behaved controlled rate di/dt waveforms with them, especially during reverse recovery in clocked designs.
Your mosfet is not so fast with Reverse recovery time at 152nS and Reverse recovery charge around 844nC which
actually increases at high temperature operation. Though in reality the charge accumulation depends on the time spent during forward path conduction of the body diode and associated parasitics plus rate of allowed di/dt which is higher in your case than the datsheet specs. Hence the flush out or reverse recovery due to short deadtime could be even faster.
Also in my experience, quadrature phased clocks are better option than anti phase clocks, one of the well known brands is doing the same as well.
Last edited:
First of all, I do not worry about sync and noises, because I have already powered this 2-channel amplifier from a smps and no noise or interference occurred. If in the final version I have some of this, I will take into account the advice to synchronize in quadrature.
I do not worry about the modulator, or the distortion at 10khz when the output signal approaches the supply voltage, because there is still a room for optimization, so far I focused on a stable response from the modulator with the load of 4-8 ohms, and without the load. Incidentally, in selfosc classD, the output without load is perfectly stable, but fixed-frequency modulators are known to have chaotic behavior at the loss of load, or the variation in the frequency of the impedance of the load, a typical case of passive multi way speaker. I think i have solved these issues quite nice, and i am not facing any kind of noises or emi issues.
I'm worried about the gate driving at hardsw condition, which seems not optimal. I mention that i have somewhere between 20-25mm between the driver and the mosfets.
I do not worry about the modulator, or the distortion at 10khz when the output signal approaches the supply voltage, because there is still a room for optimization, so far I focused on a stable response from the modulator with the load of 4-8 ohms, and without the load. Incidentally, in selfosc classD, the output without load is perfectly stable, but fixed-frequency modulators are known to have chaotic behavior at the loss of load, or the variation in the frequency of the impedance of the load, a typical case of passive multi way speaker. I think i have solved these issues quite nice, and i am not facing any kind of noises or emi issues.
I'm worried about the gate driving at hardsw condition, which seems not optimal. I mention that i have somewhere between 20-25mm between the driver and the mosfets.
Last edited:
1-deadtime 45ns, gate drive 22r with diode:
2-deadtime 75ns, gate drive 22r with diode
3-deadtime 75ns, gate drive 22r with parallel diode, and 4r7 in series with diode:
It looks like the mosfet does not close enough because of the inductive 20-25mm driver-to-mosfet distance.
This is hard switching test.
Input of the amp shorted. From output to negative rail a load resistor of 4 ohms, looks like 20a load current.
An externally hosted image should be here but it was not working when we last tested it.
2-deadtime 75ns, gate drive 22r with diode
An externally hosted image should be here but it was not working when we last tested it.
3-deadtime 75ns, gate drive 22r with parallel diode, and 4r7 in series with diode:
An externally hosted image should be here but it was not working when we last tested it.
It looks like the mosfet does not close enough because of the inductive 20-25mm driver-to-mosfet distance.
This is hard switching test.
Input of the amp shorted. From output to negative rail a load resistor of 4 ohms, looks like 20a load current.
Last edited:
I am with eva and Kanwar.
To me it does not look like an issue with the gate drive loop, but more
like the traditional issue with the parasitic inductance of the loop:
DrainOfUpperMosFet==>SourceOfUpperMosFet==>DrainOfLowerMosFet==>FilmCap==>FilmCap==>DrainOfUpperMosFet.
High di/dt of the switching events cause a voltage peak in this loop, directly following V = L *di/dt (People with Phd in physics would insist: V = - L*di/dt).
This voltage peak becomes visible accross the drain source path of the Fet which has the higher impedance in this moment.
If you have no option to reduce the inductance of this loop you will have to control di/dt. Various options where already mentioned in the postings before.
One more option which allows to adjust di/dt to any desired value I had
shown here in posting #19 & #20:
1kW Gen2
Basically this is my home brew method in case you need really slow di/dt.
Often eva's proposal to put just a longer source wire or track which is shared by the load current and the gate drive is already sufficient.
Last edited:
Thank you for your suggestions. I inserted a wire of 10 to 20mm in the source of each mosfet, knowing that it will be an inductance of 10-20nh. The scheme has become like this:
Waveforms have improved, but up to 10nh, what's over does not seem to bring any benefit.
1-low side mosfet off, idle
2-low side mosfet on, idle
3-low side mosfet on, 4r load connected to +vcc
4-low side mosfet on, 4r load connected to -vcc
5-low side mosfet off, 4r load connected to +vcc
6-low side mosfet off, 4r load connected to -vcc
An externally hosted image should be here but it was not working when we last tested it.
Waveforms have improved, but up to 10nh, what's over does not seem to bring any benefit.
1-low side mosfet off, idle
An externally hosted image should be here but it was not working when we last tested it.
2-low side mosfet on, idle
An externally hosted image should be here but it was not working when we last tested it.
3-low side mosfet on, 4r load connected to +vcc
An externally hosted image should be here but it was not working when we last tested it.
4-low side mosfet on, 4r load connected to -vcc
An externally hosted image should be here but it was not working when we last tested it.
5-low side mosfet off, 4r load connected to +vcc
An externally hosted image should be here but it was not working when we last tested it.
6-low side mosfet off, 4r load connected to -vcc
An externally hosted image should be here but it was not working when we last tested it.
The waveforms show the effect of reduced di/dt: less peaking. Now I realize you are testing the amplifier at only +/-50V, dropping to +/-40V during the 4r-to-rail tests. Alternative test is tone burst with LF square wave, for ease of oscilloscope synchronization and to keep heat under control. This mode will be required for testing the output stage at high rails and full power.
Optimization is plain engineering. Find the limiting factors. The body diode is rated for up to 1kA/us and 60V/ns, at up to 44A and 175C. The PCB is rated for 0.5kA/us maybe, to keep the inductive voltage drop across traces under control.
Average Vgs-th for OFF is about 3.8V considering the 0~40A interval and 25~125C.
Average Vgs-th for ON is about 4V considering the 0~60A interval and 25~125C. This includes +50% to account for reverse recovery current.
For about 0.5kA/us OFF a source lead inductance of 3.8V/(500A/us)=7.6nH is the target. This is about the inductance happening naturally, when lead is bent 6mm away from the package and there are no L reduction factors. The OFF diode and no OFF resistor is OK in this case. Internal gate resistance of about 2.4ohm takes care of current limiting. Drawback of this approach is that, in case the FET becomes shorted gate to drain, and source open, it will pop the driver IC too, this can be solved with adequate clamping and a low value fast fusing series element (like a SMD fuse, I don't know solution for thru-hole).
For 0.5kA/us ON an average 3.8V drop across 7.6nH source lead inductance during ON is to be aimed for. Since Vgs-th is about 4V, the average V drop across the FET itself would be 7.8V. It seems the gate drive voltage used is 12V. This leaves 4.2V from 7.8V to 12V. The average voltage drop across gate drive impedance (plus internal gate resistance) should account for those 4.2V. In practice this dictates increasing gate ON resistor a lot.
Lets do a minimum calculation:
Cg=5.5nF for this case (turn on at high Vds).
A 0A to 60A ramp translates to about 1V increase in Vgs. At 0.5kA/us this would happen in 120ns.
To charge 5.5nF up by 1V in 120ns (40A at 0.5kA/us) a current of about 46mA is needed.
To get a 4.2V drop with 46mA a total resistance of 91ohm would be needed. This compromises dv/dt and dead time. The solution is reducing gate drive supply to 10V, to change the 4.2V resistive drop target to 2.2V, which are obtained with 48ohm. This calls for a Si824xB IC with 8V UVLO.
My personal preference is externally buffering a lower current driver IC (like Si8241B in this case), as this allows: an external more rugged scheme for protecting from gate-drain shorts, a lower value for ON gate resistor due to extra V drop introduced by buffers, and other tricks. Of course this involves more parts and can worsen the power trace layout, so for a simple thru-hole design it might not be the way to go.
Optimization is plain engineering. Find the limiting factors. The body diode is rated for up to 1kA/us and 60V/ns, at up to 44A and 175C. The PCB is rated for 0.5kA/us maybe, to keep the inductive voltage drop across traces under control.
Average Vgs-th for OFF is about 3.8V considering the 0~40A interval and 25~125C.
Average Vgs-th for ON is about 4V considering the 0~60A interval and 25~125C. This includes +50% to account for reverse recovery current.
For about 0.5kA/us OFF a source lead inductance of 3.8V/(500A/us)=7.6nH is the target. This is about the inductance happening naturally, when lead is bent 6mm away from the package and there are no L reduction factors. The OFF diode and no OFF resistor is OK in this case. Internal gate resistance of about 2.4ohm takes care of current limiting. Drawback of this approach is that, in case the FET becomes shorted gate to drain, and source open, it will pop the driver IC too, this can be solved with adequate clamping and a low value fast fusing series element (like a SMD fuse, I don't know solution for thru-hole).
For 0.5kA/us ON an average 3.8V drop across 7.6nH source lead inductance during ON is to be aimed for. Since Vgs-th is about 4V, the average V drop across the FET itself would be 7.8V. It seems the gate drive voltage used is 12V. This leaves 4.2V from 7.8V to 12V. The average voltage drop across gate drive impedance (plus internal gate resistance) should account for those 4.2V. In practice this dictates increasing gate ON resistor a lot.
Lets do a minimum calculation:
Cg=5.5nF for this case (turn on at high Vds).
A 0A to 60A ramp translates to about 1V increase in Vgs. At 0.5kA/us this would happen in 120ns.
To charge 5.5nF up by 1V in 120ns (40A at 0.5kA/us) a current of about 46mA is needed.
To get a 4.2V drop with 46mA a total resistance of 91ohm would be needed. This compromises dv/dt and dead time. The solution is reducing gate drive supply to 10V, to change the 4.2V resistive drop target to 2.2V, which are obtained with 48ohm. This calls for a Si824xB IC with 8V UVLO.
My personal preference is externally buffering a lower current driver IC (like Si8241B in this case), as this allows: an external more rugged scheme for protecting from gate-drain shorts, a lower value for ON gate resistor due to extra V drop introduced by buffers, and other tricks. Of course this involves more parts and can worsen the power trace layout, so for a simple thru-hole design it might not be the way to go.
Last edited:
That can help but it also can increase nonlinear distortions. At the currents at the target power level saturation will probably happen and even if it doesn't, the hysteresis of the beads could affect the amp negatively. What works with smaller amps is not necessarily scalable.
After several optimizations, I connected the amplifier to +/- 105v with a toroidal transformer, the load resistor in hardswitching mode being 4 ohms. Following the displayed voltages, which take into account the voltage drop in the load, a load current of 44-48 amps results. Waveforms appear much cleaner now, and considering that I could also reduce the dead time in the si8244 driver to a value of 25ns, I'm happy with the result. The change consists in a source inductor of 7-9nh, but also increasing value of gating resistor from 22 ohms to 47 ohms.
As I have used to you, here are the measured waveforms:
1-low side mosfet on, 4r load connected to +vcc
2-low side mosfet on, 4r load connected to -vcc
3-low side mosfet off, 4r load connected to +vcc
4-low side mosfet off, 4r load connected to -vcc
As I have used to you, here are the measured waveforms:
1-low side mosfet on, 4r load connected to +vcc
An externally hosted image should be here but it was not working when we last tested it.
2-low side mosfet on, 4r load connected to -vcc
An externally hosted image should be here but it was not working when we last tested it.
3-low side mosfet off, 4r load connected to +vcc
An externally hosted image should be here but it was not working when we last tested it.
4-low side mosfet off, 4r load connected to -vcc
An externally hosted image should be here but it was not working when we last tested it.
