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Class D Switching Power Amplifiers and Power D/A conversion

Class D amp with 300v mosfets
Class D amp with 300v mosfets
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Old 9th October 2017, 03:13 AM   #11
Workhorse is offline Workhorse
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Ionut,

Try ferrite beads over the gate and drain legs, I have achieved very well behaved controlled rate di/dt waveforms with them, especially during reverse recovery in clocked designs.

Your mosfet is not so fast with Reverse recovery time at 152nS and Reverse recovery charge around 844nC which
actually increases at high temperature operation. Though in reality the charge accumulation depends on the time spent during forward path conduction of the body diode and associated parasitics plus rate of allowed di/dt which is higher in your case than the datsheet specs. Hence the flush out or reverse recovery due to short deadtime could be even faster.

Also in my experience, quadrature phased clocks are better option than anti phase clocks, one of the well known brands is doing the same as well.

Last edited by Workhorse; 9th October 2017 at 03:19 AM.
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Old 9th October 2017, 06:26 AM   #12
ionutgaga is offline ionutgaga
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First of all, I do not worry about sync and noises, because I have already powered this 2-channel amplifier from a smps and no noise or interference occurred. If in the final version I have some of this, I will take into account the advice to synchronize in quadrature.
I do not worry about the modulator, or the distortion at 10khz when the output signal approaches the supply voltage, because there is still a room for optimization, so far I focused on a stable response from the modulator with the load of 4-8 ohms, and without the load. Incidentally, in selfosc classD, the output without load is perfectly stable, but fixed-frequency modulators are known to have chaotic behavior at the loss of load, or the variation in the frequency of the impedance of the load, a typical case of passive multi way speaker. I think i have solved these issues quite nice, and i am not facing any kind of noises or emi issues.
I'm worried about the gate driving at hardsw condition, which seems not optimal. I mention that i have somewhere between 20-25mm between the driver and the mosfets.

Last edited by ionutgaga; 9th October 2017 at 06:31 AM.
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Old 9th October 2017, 07:51 AM   #13
ionutgaga is offline ionutgaga
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1-deadtime 45ns, gate drive 22r with diode:
Click the image to open in full size.

2-deadtime 75ns, gate drive 22r with diode
Click the image to open in full size.

3-deadtime 75ns, gate drive 22r with parallel diode, and 4r7 in series with diode:
Click the image to open in full size.

It looks like the mosfet does not close enough because of the inductive 20-25mm driver-to-mosfet distance.

This is hard switching test.
Input of the amp shorted. From output to negative rail a load resistor of 4 ohms, looks like 20a load current.

Last edited by ionutgaga; 9th October 2017 at 07:54 AM.
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Old 9th October 2017, 06:58 PM   #14
ChocoHolic is offline ChocoHolic  Germany
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Quote:
Originally Posted by ionutgaga View Post
I'm worried about the gate driving at hardsw condition, which seems not optimal. I mention that i have somewhere between 20-25mm between the driver and the mosfets.
I am with eva and Kanwar.
To me it does not look like an issue with the gate drive loop, but more
like the traditional issue with the parasitic inductance of the loop:
DrainOfUpperMosFet==>SourceOfUpperMosFet==>DrainOf LowerMosFet==>FilmCap==>FilmCap==>DrainOfUpperMosF et.
High di/dt of the switching events cause a voltage peak in this loop, directly following V = L *di/dt (People with Phd in physics would insist: V = - L*di/dt).
This voltage peak becomes visible accross the drain source path of the Fet which has the higher impedance in this moment.
If you have no option to reduce the inductance of this loop you will have to control di/dt. Various options where already mentioned in the postings before.

One more option which allows to adjust di/dt to any desired value I had
shown here in posting #19 & #20:
1kW Gen2
Basically this is my home brew method in case you need really slow di/dt.
Often eva's proposal to put just a longer source wire or track which is shared by the load current and the gate drive is already sufficient.

Last edited by ChocoHolic; 9th October 2017 at 06:59 PM. Reason: typos
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Old 10th October 2017, 11:31 AM   #15
ionutgaga is offline ionutgaga
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Thank you for your suggestions. I inserted a wire of 10 to 20mm in the source of each mosfet, knowing that it will be an inductance of 10-20nh. The scheme has become like this:
Click the image to open in full size.

Waveforms have improved, but up to 10nh, what's over does not seem to bring any benefit.

1-low side mosfet off, idle
Click the image to open in full size.

2-low side mosfet on, idle
Click the image to open in full size.

3-low side mosfet on, 4r load connected to +vcc
Click the image to open in full size.

4-low side mosfet on, 4r load connected to -vcc
Click the image to open in full size.

5-low side mosfet off, 4r load connected to +vcc
Click the image to open in full size.

6-low side mosfet off, 4r load connected to -vcc
Click the image to open in full size.
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Old 10th October 2017, 01:02 PM   #16
Eva is offline Eva  Spain
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The waveforms show the effect of reduced di/dt: less peaking. Now I realize you are testing the amplifier at only +/-50V, dropping to +/-40V during the 4r-to-rail tests. Alternative test is tone burst with LF square wave, for ease of oscilloscope synchronization and to keep heat under control. This mode will be required for testing the output stage at high rails and full power.

Optimization is plain engineering. Find the limiting factors. The body diode is rated for up to 1kA/us and 60V/ns, at up to 44A and 175C. The PCB is rated for 0.5kA/us maybe, to keep the inductive voltage drop across traces under control.

Average Vgs-th for OFF is about 3.8V considering the 0~40A interval and 25~125C.

Average Vgs-th for ON is about 4V considering the 0~60A interval and 25~125C. This includes +50% to account for reverse recovery current.

For about 0.5kA/us OFF a source lead inductance of 3.8V/(500A/us)=7.6nH is the target. This is about the inductance happening naturally, when lead is bent 6mm away from the package and there are no L reduction factors. The OFF diode and no OFF resistor is OK in this case. Internal gate resistance of about 2.4ohm takes care of current limiting. Drawback of this approach is that, in case the FET becomes shorted gate to drain, and source open, it will pop the driver IC too, this can be solved with adequate clamping and a low value fast fusing series element (like a SMD fuse, I don't know solution for thru-hole).

For 0.5kA/us ON an average 3.8V drop across 7.6nH source lead inductance during ON is to be aimed for. Since Vgs-th is about 4V, the average V drop across the FET itself would be 7.8V. It seems the gate drive voltage used is 12V. This leaves 4.2V from 7.8V to 12V. The average voltage drop across gate drive impedance (plus internal gate resistance) should account for those 4.2V. In practice this dictates increasing gate ON resistor a lot.

Lets do a minimum calculation:
Cg=5.5nF for this case (turn on at high Vds).
A 0A to 60A ramp translates to about 1V increase in Vgs. At 0.5kA/us this would happen in 120ns.
To charge 5.5nF up by 1V in 120ns (40A at 0.5kA/us) a current of about 46mA is needed.

To get a 4.2V drop with 46mA a total resistance of 91ohm would be needed. This compromises dv/dt and dead time. The solution is reducing gate drive supply to 10V, to change the 4.2V resistive drop target to 2.2V, which are obtained with 48ohm. This calls for a Si824xB IC with 8V UVLO.

My personal preference is externally buffering a lower current driver IC (like Si8241B in this case), as this allows: an external more rugged scheme for protecting from gate-drain shorts, a lower value for ON gate resistor due to extra V drop introduced by buffers, and other tricks. Of course this involves more parts and can worsen the power trace layout, so for a simple thru-hole design it might not be the way to go.
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Last edited by Eva; 10th October 2017 at 01:06 PM.
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Old 11th October 2017, 12:07 AM   #17
ICG is offline ICG  Germany
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Quote:
Originally Posted by Workhorse View Post
Try ferrite beads over the gate and drain legs, I have achieved very well behaved controlled rate di/dt waveforms with them, especially during reverse recovery in clocked designs.
That can help but it also can increase nonlinear distortions. At the currents at the target power level saturation will probably happen and even if it doesn't, the hysteresis of the beads could affect the amp negatively. What works with smaller amps is not necessarily scalable.
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Old 11th October 2017, 07:35 AM   #18
Workhorse is offline Workhorse
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Quote:
Originally Posted by ICG View Post
That can help but it also can increase nonlinear distortions. At the currents at the target power level saturation will probably happen and even if it doesn't, the hysteresis of the beads could affect the amp negatively. What works with smaller amps is not necessarily scalable.
Do you have measurements, waveform data to enlighten us about the very effect you are talking about, since I fail to see a rise in distortion in my multi kilowatt module with ferrite beads. We might learn something new from you?
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Old 11th October 2017, 12:48 PM   #19
ionutgaga is offline ionutgaga
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After several optimizations, I connected the amplifier to +/- 105v with a toroidal transformer, the load resistor in hardswitching mode being 4 ohms. Following the displayed voltages, which take into account the voltage drop in the load, a load current of 44-48 amps results. Waveforms appear much cleaner now, and considering that I could also reduce the dead time in the si8244 driver to a value of 25ns, I'm happy with the result. The change consists in a source inductor of 7-9nh, but also increasing value of gating resistor from 22 ohms to 47 ohms.
As I have used to you, here are the measured waveforms:

1-low side mosfet on, 4r load connected to +vcc
Click the image to open in full size.

2-low side mosfet on, 4r load connected to -vcc
Click the image to open in full size.

3-low side mosfet off, 4r load connected to +vcc
Click the image to open in full size.

4-low side mosfet off, 4r load connected to -vcc
Click the image to open in full size.
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Old 11th October 2017, 03:21 PM   #20
Khron is offline Khron  Finland
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Just as a side-note, since i see a USB connector on the front of that scope, wouldn't it be simpler(?) to do screenshots from the scope itself? That would at least eliminate screen glare from outside light sources.
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