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Old 24th November 2012, 10:24 AM   #11
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Choco,

I did a lame attempt on discrete comparator, results are ok, but the comparator fall time is not same as rise time, need to work on that, have a look.
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Old 24th November 2012, 10:26 AM   #12
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Hi Kanvar,
I am loving your rookie attempt!
The second one is looking great and might outperform your earlier work,
but it does not have this special DIY feeling like your first.

Discrete Comparator:
Hm, you are also a fan of this?
I detected the integrated comparators and their jitter mechanisms as one of
the key contributors to poor noise figures. And because of this I build the comparator in discrete for SystemD_MD.
The downside is that this is one of the most effective ways to boost the component count and by this reducing the chances for other DIYers to get their build running.
In the mean time I understood and learned how to tame the jitter a little bit.
I can implant a LM360 in the SystemD MD and still derive reasonably good noise figures, about 10db worse than with my discrete comparator.

Basically my intension of this amp is to design it in a DIY-friendly way.
That's why I intended to go for an integrated comparator.
Also for the output devices I am intending to live with the short comings of the TO247 and use IRFP4668 instead of paralleling multiple IRFB4227...
Do you think I should change this overall direction?
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Old 24th November 2012, 10:38 AM   #13
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Just remember that UCD is fully discrete and easily made by many Diyers here.

Yes , i love discrete comparators, because even i have seen the SNR levels increase[less jitter, less noise] with them and using chip solutions annoys you in results.

Its always better to use a single device rather than paralleling, I know TO-220 lead inductance is lower than TO-247 but then more devices makes the layout more critical which has adverse impact on DIYing.

One can make both versions, for users wanting to step into more depth, discrete version could do, for easy doers the chip comp will be sufficient.
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Old 24th November 2012, 02:16 PM   #14
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From my understanding there is a fundamental difference in the comparator requirements between UcD and hysteresis oscillators.
For UcD you need a chain of comparator and power stage which has to have a long delay in order avoid unsaint high switching frequencies. Also low comparator gain is helpful.
In the inteded circuit I dislike the hidden intrinsic parasitic phase shift self oscillator, because it impacts the intended mode of operation. So I prefer to have a chain with low delay and exact switching points, which is making the comparator design more extensive....

Nevertheless the idea to think about options to enable both is good.
In case the LM360 would become annoying, it should be possible to design a discrete comparator that fits to the DIL8 socket of the LM360 plus two wires for +/-12V.

Attached a simplified schematic of the amp from which the earlier simulations were derived.
I already have a sim with more detailed power stage including IRFP4668, but so far I have no reasonable option to post larger schematics in a readable way...

The overall structure is very similar to System_MD.
- table E3 can be any reasonably fast OP amp, which is stable at gains >3.
Design goal: Allow to use 1/2 NE5532.
- Q3, Q4 provide the virtual GND for the D portion of the feedback
- table E1 should be the LM360
- table E2 is the level shifter (IRS20957) and BJT gate buffer and IRFP4668
- In front of the shown amp the second half of the NE5532 will be put as an differential input amp to enable symmetric inputs and easy amp bridging.
- Upgrading the circuit with better OPamps possible.

The connection point for the hyteresis control circuit links to the previously shown circuit.

With these values the amp has an idle frequency of 315kHz in simulation.
I am also considering higher frequencies, but from theory the switching losses in case of a short circuit with small input signals, which can run the amp with unreduced frequency close to the overcurrent shut down, but just not triggering it - are already at the limits of the SOA of the IRFP4668.
2kW, 80V rails and an overcurrent protection around 60A demand their tribute...
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Old 24th November 2012, 02:27 PM   #15
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Quote:
Originally Posted by Workhorse View Post
Choco,

I did a lame attempt on discrete comparator...
Not a lame attempt at all. I did not see this posting earlier, because I was writing my posting at the same time.
I cannot see all details of the circuit, but it looks like a typical straight forward design which allows reasonably results.
From my findings symmetric delays and rise times can be achieved best by an a fully symmetric approach... again more components.
Most simple a fully symmetric input stage of such an comparator can be achieved by using JFets instead of BJTs, because their control characteristic allow simple self biasing.
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Old 24th November 2012, 03:24 PM   #16
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Quote:
Originally Posted by darkfenriz View Post
...
Adjusting hysteresis window to get tighter switching frequencies range is scary. ...
From my side, I think I can contribute to this open design in certain parts of modulator circuitry, switching part and layout if you'd wish.
..
Hi Adam,
of course I welcome your input !
It might bring me to the trouble to decide whether I should try your ideas or my ideas and I might not always find the time to elaborate in proper detail on both.
Why is a dynamic hysteresis scary?
...such discussion is what I enjoy....
In case we have two parallel ideas, which we both would love to see in reality - it might be even cooler to derive two design versions. You are living in EU, so exchange even of components and PCBs should be possible in an easy way...

Btw: What happened with your genious bridgeable fullbridge?


...back to the discrete Comparator:
Attached a sketch of a simple discrete approach, which should just satisfy the needs and still would be possible with reasonable component count.
It has similarities to the design in MD, but in MD I used a MosFet input which does not allow for easy self biasing....
So the attached version should be more DIYable (except obsolete components).
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Old 24th November 2012, 05:54 PM   #17
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Quote:
Originally Posted by Workhorse View Post
Choco,

... have a look.
I am guessing what is displayed there, but a zoom of the circuit without sim results would be helpful.
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Old 24th November 2012, 06:18 PM   #18
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Quote:
Originally Posted by ChocoHolic View Post
I am guessing what is displayed there, but a zoom of the circuit without sim results would be helpful.
Just uploaded the sim file, i hope you have LTC
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File Type: jpg compo.jpg (82.8 KB, 1152 views)
Attached Files
File Type: asc my own thing.asc (13.6 KB, 30 views)

Last edited by Workhorse; 24th November 2012 at 06:33 PM.
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Old 24th November 2012, 06:28 PM   #19
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Default Great going Choco

I think a Hysteresis modulator with a CCS control [i have seen this approach somewhere] is best option in order to mitigate any effects of voltage fluctuations. This will give more precision and control over how it actually performs.

Quote:
Originally Posted by ChocoHolic View Post
Nevertheless the idea to think about options to enable both is good.
In case the LM360 would become annoying, it should be possible to design a discrete comparator that fits to the DIL8 socket of the LM360 plus two wires for +/-12V.

Attached a simplified schematic of the amp from which the earlier simulations were derived.
I already have a sim with more detailed power stage including IRFP4668, but so far I have no reasonable option to post larger schematics in a readable way...
Supply voltage limit for LM360 is recommended at +/-6V max not +/-12V, for that you need LM361. Also the IRFP4668 in bridge format is capable of more than 4KW in 2 ohms music[been there done that]

Quote:
Originally Posted by ChocoHolic View Post
Not a lame attempt at all. I did not see this posting earlier, because I was writing my posting at the same time.
I cannot see all details of the circuit, but it looks like a typical straight forward design which allows reasonably results.
From my findings symmetric delays and rise times can be achieved best by an a fully symmetric approach... again more components.
Most simple a fully symmetric input stage of such an comparator can be achieved by using JFets instead of BJTs, because their control characteristic allow simple self biasing.
I agree with you that a symmetric section is always needed for symmetric slewrate. Will be doing some more sims in short while.

Quote:
Originally Posted by ChocoHolic View Post
back to the discrete Comparator:
Attached a sketch of a simple discrete approach, which should just satisfy the needs and still would be possible with reasonable component count.
It has similarities to the design in MD, but in MD I used a MosFet input which does not allow for easy self biasing....
So the attached version should be more DIYable (except obsolete components).
Don't you think matching of JFETs is little critical, or one can get away with that in case of comparators.?
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Old 24th November 2012, 07:25 PM   #20
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12V-Misunderstanding:
I am planning to run the LM360 with +/-5V, output stage with 5V only, of course.
But the discrete solution will need the +/-12V rails (or something like this),
which are not available on the DIL8 socket of the LM360, so there the two additional wires for the discrete plugin would be necessary.

SOA:
Of course the IRFP4668 can handle more than 4kW, especially when used at lower frequencies. And of course you will find plenty designs that do not consider worst case situations and also no theoretical SOA check at all.
When looking to selfoscillating class D amps, then the critical situation will never be normal operation, because you only have the high currents at high modulation levels where you have low switching frequencies. This is definitely a very fortunate nature of the selfoscillating designs.
But when looking to the described worst case scenario:
-Output running into a shorted wire ==> i.e. 50m Ohms
-Input signal small, but enough to go for approx. 3V output into 50m Ohms
Then you will still have the high switching frequency and 60Amax and almost no rail sagging ==> That's the worst case scenario.
Well, so far the theory. In practise I came to the conclusion that the IR devices are tough ones and making full use of the SOA, instead of keeping hypochondric margins, never caused any issues. In fact on my workbench they even took overload situations moderately beyond the theoretic SOA considerations with a smile....
Coming from this and fitting to your comment, I might give a chance to my 400kHz version, because it simply offers noticeable better performance.

JFET-matching:
You are right, massively unmatched devices might cause issues.
But I think it should be easy fit them in a sufficient way.
We do not need offset perfection, just a reasonable bias situation when the output is its linear region.
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