single ended ucd with gain of 1

[switchleg]

I have been doing a bunch simulations. The best thd and dc off results seem to come from running it from a discrete class a input single ended where all the gain is from the class a amp and having a gain of 1 in the class d stage. Schematics being the same as running it from a balance input with a gain of 4.5 in the balanced differential stage and 4 in the class d stage.... anyone ever tried this on a board?

 

[Bigun]

sounds interesting - I think the combination of a class A gain stage feeding a class D buffer is a very attractive idea. What does your Class D buffer look like ?

 

[switchleg]

as you can see the feedback network is very standard other then the input is using a darlington pair. even with a standard input i seem to get best results with it being ran single ended with using the ucd as a buffer only (due to what seems to be less change in modulation frequency)... though im not sure how it will stack up in the real world.

I also have another design that pspice simulations show that will help resolve thermal drift and keep the comparator balanced... still yet to see it online anywhere so i am about a couple hours from throwing the board through the acid to find out

btw i only use irf530n for simulating as its difficult to find models for any decent new FETS.