Tekko goes crazy

[Pafi]

And my class d amp has so much deadtime that even the carrier residual after the output filter has crossover distortion kinks in it.

I don't know any connection between residual and dead time. Can you explain it?

Why not just tell the value?

[Tekko]

I don'r know the value, i have no way of measuring suth thing.

[Pafi]

I saw a modern oscilloscope on your video.

[ChocoHolic]

Originally Posted by Pafi

Reverse recovery charge can't be higher than the stored charge

Yupp, I trust in this from theory and measurements as well.
Could be the key reason, which might give Tekko's power stage a chance to survive at higher power levels.
..curious, how this story goes on!

[darkfenriz]

That mosfet is from 1993.
Life used to be quite tough back then, I imagine the internal parasitic bipolar transistor just sitting there and waiting to do a kaboom!

Seriously, the body diode charge is a function of pretty much everything and most 'mainstream' manufacturers document it in a very bad way, at nearly full rated current, after full forward charge build-up and at nonsense 100A/us. JEDEC norms take a part of a blame, still I am waiting until they learn how to document it properly...

[ChocoHolic]

Originally Posted by darkfenriz

imagine the internal parasitic bipolar transistor just sitting there and waiting to do a kaboom!

The data sheet does not specify a limitation for dv/dt.
...it feels so good to believe that there is no limitation...

[ChocoHolic]

...and even in this regard Tekko's design might surprise positively...
Crss is forming a dv/dt limiter with the gate drive impedance.
Even when we consider the turn OFF is pulled down through the gate drive diode with max capability of the IR21xxx, we can expect that the system limits itself to a max dv/dt around 900V/us (assuming approximately 5 Ohms internal impedance of the IR21xxx).

900V/us is sounding trouble free even for such old devices.

[darkfenriz]

Yes, I agree it can well never happen, but if it is about to happen there are no warnings

I am not sure about your calcs, if one assumes dv/dt=i/C, i=2A (ir2110 out) and C=1nF (Crss gets lower at rising Vds!!) it looks like 2000V/us. Still not very scary though.

edit: what if gate full turn-on time is much shorter than trr? Is Crss still a limiting factor?

[Tekko]

This is the cirduit of the amp as of today: http://i.imgur.com/jiG2g.png

I removed the capacitors on the comparator outputs that i used to generate deadtime and added 1µF 0805 capacitors petween gnd and the two 5v rails right at the pins of the comparators and the triangular wave gen opamp.

I also joined pin 5 and 6 of the comparators and put a 1µF 0805 cap between these and GND to prevent them picking up noise and cause false triggering.

It does now seem to work better and happily pushes 10A into a 1 ohm load without complaining, i havent gone any further as its really daggone loud.

I'll do some tests with a dummyload at a later stage.

[ChocoHolic]

Originally Posted by darkfenriz

I am not sure about your calcs, if one assumes dv/dt=i/C, i=2A (ir2110 out) and C=1nF (Crss gets lower at rising Vds!!) it looks like 2000V/us. Still not very scary though.

I also calculated with 1nF, because it is specified at 25V, which is a reasonable point somewhere in middle of the non linear characteristic..

I think the IR21xxx has a Fet output stage, so the 2.5A (which is the specified max. output current into a short) translates to an output impedance of 15V/2.5A=6 Ohms.
For calculation I have chosen 5 Ohms, in order to cover uncertainties of the linearity of the output impedance - and it is easier to calculate.
The data sheet of the Fet shows a gate plateau around 4.5V, means somewhere around that the MosFet changes from low impedances to high impedances.
If gate driver pulls down with 5 Ohms, then it would need a current through Crss of I=4.5V/5 Ohms=0.9A in order pull the gate up to 4.5V.
0.9A through 1nF translates to dv/dt=900V/us.
I neglected the diode in the gate pull down, consequently already slighlty lower dv/dt might deliver the balance of this dv/dt limiter.

Originally Posted by darkfenriz

edit: what if gate full turn-on time is much shorter than trr? Is Crss still a limiting factor?

I think you already answered this on your own.
Specified trr is not the key value, because like Qrr it is defined at values that are different from the application. di/dt is different and in Tekko's application we will most likely not have the junction fully flooded.
Let's talk about the application specific reverse recovery time.
If the pulse is much shorter and you have the hard switching situation you won't have much dv/dt. Uds is sticking completely stubborn to low values until the charge is removed from the junction.
Means, very short pulses might cause nothing but heat in the opposite MosFet.


@Tekko:
Your approach of reducing the dead time appears reasonable to me.
The IR itself will not provide much of a dead time in your new set up, but the output impedance and R-D-configuration in combination with the gate properties and the level of driver supply rail will deliver sort of an analogue soft dead time (or should we call it transition characteristic ?).
Take care, especially at higher driver supply and low resistor values you can get overlap/shoot through.
With simple methods you can optimize your dead time by measuring the idle current consumption of the power stage. When you reduce the dead time more and more you will reach a point where the idle current consumption starts to increase rapidly. Stay close to this point and you are close to the optimum.
Enjoy riding your cannonball !!