Incorrect fetdriving?

[Blackdrake]

Hi folks,

I'm busy trying to understand fetdriving.
I tried something in Multisim v10.0



This seems to work a bit, but the highside does have a lower amplitude as the lowside.
Any suggestions how to improve this schedule, or which schedule to use otherwise?

My class D is single supplied with 120Vdc.
I have to get 1500W in a 4ohm load.

I'm not a very experienced user of class D equipment, so please try to explain things simple.

[lorylaci]

Firs of all: the supply for the high side FET should be floating!
The level shift also bad, see some application notes first.

[Blackdrake]

Originally Posted by lorylaci

Firs of all: the supply for the high side FET should be floating!
The level shift also bad, see some application notes first.

Where should the - of the floating supply connected?
And where do I find decent application notes?
I found some application notes, but they're not to helpfull

[Osvaldo de Banfield]

The upper transistor, operating as common base is bad biased. And the diode at the collector of the driver is unnecessary.

Why not to try IR2110?

[Blackdrake]

If I understood you guys right, this should be an improvement,
Though I can't find anything about the 'bad-biasing' you spoke about.
I found some application notes, which are poorly explained and because of that not to helpfull.

The only thing I got from those apllication notes, is seeing that they use 2 FETs instead of BJTs.



The schedule with some adjustments.

[lorylaci]

Originally Posted by Blackdrake

Where should the - of the floating supply connected?
And where do I find decent application notes?
I found some application notes, but they're not to helpfull

Read this:
http://www.ti.com/lit/ml/slup169/slup169.pdf
From page 22 starts the bootstrap drive.

[Blackdrake]

Thank you for that link, there is quite some usefull information in it, though I have no clue how to implement it into my schedule.
I also checked the IR2011, which seems easier to get working in a practical situation.

I'll be busy for a bit with the new information for a while, if I encounter more problems I will post them right away.

Class D is still witchcraft to me afterall.

[Osvaldo de Banfield]

Originally Posted by Blackdrake

Though I can't find anything about the 'bad-biasing' you spoke about.

In the first circuit, base is more positive than collector, so it has no room to amplify, then upper MOS is not well drive.

[lorylaci]

Originally Posted by Blackdrake

Thank you for that link, there is quite some usefull information in it, though I have no clue how to implement it into my schedule.
I also checked the IR2011, which seems easier to get working in a practical situation.

I'll be busy for a bit with the new information for a while, if I encounter more problems I will post them right away.

Class D is still witchcraft to me afterall.

Read, Read and Read more... until it's is aint witchcraft.

[Blackdrake]

Originally Posted by lorylaci

Read, Read and Read more... until it's is aint witchcraft.

I will for sure, I think the first knowledge is starting to come:




Simulation of Loadvoltage and Loadcurrent