PCM to PWM conversion 101

[percy]

Hi,
I would like to learn more about PCM to PWM conversion. The theory and implementation basics. Old fundamentals, New developments/improvments/ideas. Any good links or books I can check out ?
Thanks.

[benb]

Looks like 95 views and no responses. I kinda wonder about this myself, so I'll start this off. I googled:
PCM to PWM conversion - Google Search
The first hit is an older diyaudio thread.

Just thinking offhand, it might work better to convert not to PWM, but rather to a single-bit high-bit-rate (in the MHz range) "PCM", as used in the first stage of many sigma-delta converters. This makes the output quantized (the output always switches on a clock transition) just like DSD, but this might have a substantially higher switching frequency than Class D generally uses, causing some problems with output device switching speeds.

The volume would be controlled while in PCM (because I don't think it's readily doable as a 1 bit signal) - just multiply by a constant. With a 24-bit volume control word and a 24-bit PCM signal, the result is 48 bits which can probably be chopped (do bit reduction) back down to the 24 most significant bits without (much) audible damage, though it would be easy enough to add low-level dithering noise before the chop. If the source is 16 bits, make that 16 bits the most significant bits in a 24 bit word, then proceed as described.

Thesedays the faster 32-bit processors or microcontrollers (such as the latest ARM chips) should be fast enough to do the needed DSP work at 24/96 or so, though dedicated DSP chips are cheap enough as well.

[gmarsh]

I've done this professionally for a high power broadcast application. Things you need to know...

Doing digital generation of traditional PWM (comparing a triangle wave to your input signal) while maintaining 'audiophile' quality requires a brutally high PWM sampling rate. Technically Fs * 2^16 or >2GHz for 44.1KHz audio.

Doing noise shaping, you can gain a few bits back in the audio frequency band and bring the PWM generation frequency down to a 'practical' level - eg, 500MHz using the DDR outputs of a FPGA running at 250MHz. You can also add more PWM output channels and sum their outputs together, gaining an extra bit every time you double the number of PWM outputs.

You're better off ditching classical PWM and making a delta sigma modulator, with some tricks added like dynamic hysteresis to keep the switching frequency in a good place.

But in the end, digitally generated PWM will be limited in performance by power supply rejection/pumping, thermal effects due to output stage Rds(on), etc... effects which will likely overwhelm time quantization noise. You need to either sample your power supply voltage at a high rate with low delay to do feed forward compensation, sample the power stage output and do NFB, again with a brutally low delay... or characterize the response of your system, build a model for everything and do precorrection.

Best chip to develop such a thing would be a FPGA. Something like a Xilinx Spartan3-200A, which can run at a couple hundred MHz and has plenty of available multiplier blocks inside.

[gmarsh]

For an example of something that works, there's plenty of literature out there for building a PCM to DSD encoder. Bruno Putzeys also designed a high power DSD DAC and has an IEEE paper on it. The two blocks put together should create something sensible.