The Uber eGaN Half-Bridge Module

[EPCguy]

Originally Posted by elevator

Thanks EPCguy,
the diodes are a desperate measure. Somebody here remarked that 5V on the gate would kill the mosfets instantly, but OTOH the LM5113 wants at least 4.5V as Vdd. With Vdd=4.5V minus the diode drop, the mosfets would hopefully only go into a coma
Noted re the substrate connection.
I also found that the LM5113 already pulls down the two inputs (HI and LI) so the two resistors are not needed.
E

Elevator,
It is not as bad as all that . The abs max is 6V, but the gate leakage will start to increase beyond 5.5V. Initial 'discrete' driver boards were built with 5.6V supply and two 'matching' diodes - such that both low side and high side supplies are ~5V (EPC10XX devices required 5V for full enhancement).
EPC20XX devices are ok with 4.5V-5V and will even work at 4V for reasonable currents (plateau voltage not close to 4V). The LM5113 has an internal bootstrap diode and 5V on the supply will yield ~4.5V on the high side.

Adding a diode in series with the gate IMO makes a peak detector. With high Q this can lead to higher gate voltages (maybe?). The LM5113 pull up is 2Ohm internal and adding a series resistor will allow you to damp to the gate loop Q, such that 2Rgateloop>=Sqrt(Lgateloop/Ciss). This becomes harder for small devices and large gate loops (so keep the loop small and use wide/short traces). The gate resistance of the die is hard to measure, but ~0.6Ohm is a good WAG.

The Miller Ratio on these parts are worse than we'd like (i.e. >1), so a low impedance pull down is a must - especially the 100V/200V parts. This is why the LM5113 has a 0.5Ohm pull down. I'd suggest no series resistor for the pull down and again a short/wide trace as possible.

Hope this helps!..

[elevator]

Originally Posted by EPCguy

Elevator,
It is not as bad as all that . [..] EPC20XX devices are ok with 4.5V-5V and will even work at 4V for reasonable currents (plateau voltage not close to 4V). The LM5113 has an internal bootstrap diode and 5V on the supply will yield ~4.5V on the high side.
Hope this helps!..

Good info, EPCguy. Seeing your nick, may we assume this comes straight from the horse's mouth?
Thanks in any case
E
PS re the substrate connection to source: I assume this is more a matter of bias rather than real working current?

[EPCguy]

Originally Posted by elevator

Good info, EPCguy. Seeing your nick, may we assume this comes straight from the horse's mouth?
Thanks in any case
E
PS re the substrate connection to source: I assume this is more a matter of bias rather than real working current?

Hi Elevator,
Not sure why none of the emoticons are showing in my responses.
Yes, I'm a guy at EPC

The substrate current is much smaller than the device current, but can still peak at 1A, depending on dV/dt due to its capacitive coupling to the device. During 'hard' switching the Coss discharge/charge current can be as high as 15A.

[luka]

Originally Posted by EPCguy

Hi Elevator,
Not sure why none of the emoticons are showing in my responses.
Yes, I'm a guy at EPC

The substrate current is much smaller than the device current, but can still peak at 1A, depending on dV/dt due to its capacitive coupling to the device. During 'hard' switching the Coss discharge/charge current can be as high as 15A.

Cool, welcome

[smms73]

Originally Posted by EPCguy

Hi Elevator,
Yes, I'm a guy at EPC

welcome.

I have some questions for you, if you don't mind

In your demo boards (EPC9002), you only delay the turn on of the low fet , in the hi fet you use a Zero ohms resistor for R4, this is a typo ??

with a resistor of 2k and 10p for the capacitor the turn on delay is around 15ns, is this the recommended value or we can go lower?

what is the effective dead time, for the demo board?

The lm5113 uses a voltage clamp for the hi driver, because of the diode forward voltage drop of the low fet. but in your discrete solution you don't use none, do you have problems ?? or the conduction time of the low diode is to short to cause problems??

ok. now a tip . The specifications of this fet are very good for class d use, but this type of package scares the potential users, I know you have to use this for minimize the parasitic inductance's, that can cause problems with the Vgs limitation , so the best solution is a driver integrated with the fets, do you have plans for this, if you do, can you speak a litle about your plans.

sorry about the many questions , and i have more... next time

[smms73]

Originally Posted by elevator

Cool.
No snubbers? Or gate resistors?
E

Hi Elevator.
It uses a gate pull-up resistance (0402) but not a sink resistance because of the problem EPCguy explain in the post #41 (preventing the Vgd charge to turn the low fet on wen the hi fet turns on).

This is not a final pcb, it just have the sensible parts on it, i am thinking on include the dead time control.

[elevator]

Originally Posted by smms73

Hi Elevator.
It uses a gate pull-up resistance (0402) but not a sink resistance

Sorry I didn't see the source (pull-up) resistors. Maybe you could post the schematics as well?

Originally Posted by smms73

i am thinking on include the dead time control.

yeah, good thinking because dead time control is part of the tight timing environment.
Unfortunately it takes pins, because you'd want to be able to set dead times from the outside: look at this
(attached)..

Originally Posted by smms73

...so the best solution is a driver integrated with the fets...

That's what we're doing here, DOH!

[EPCguy]

Originally Posted by smms73

In your demo boards (EPC9002), you only delay the turn on of the low fet , in the hi fet you use a Zero ohms resistor for R4, this is a typo ??
with a resistor of 2k and 10p for the capacitor the turn on delay is around 15ns, is this the recommended value or we can go lower?
what is the effective dead time, for the demo board?
The lm5113 uses a voltage clamp for the hi driver, because of the diode forward voltage drop of the low fet. but in your discrete solution you don't use none, do you have problems ?? or the conduction time of the low diode is to short to cause problems??

ok. now a tip . The specifications of this fet are very good for class d use, but this type of package scares the potential users, I know you have to use this for minimize the parasitic inductance's, that can cause problems with the Vgs limitation , so the best solution is a driver integrated with the fets, do you have plans for this, if you do, can you speak a litle about your plans.

sorry about the many questions , and i have more... next time

Thx for the warm welcome. I'll try to answer as much as I can.

EPC9002 - the RCD pulse width adjust needs to adjust the required device deadtime as well as the mismatch in propagation delay (high side opto - no opto low side). It turns out I do not need to increase the HS pulse width - only delay and lengthen low side - therefore 'zero' on the HS adjust. Deadtime is relatively large for class-D (5-10ns) and can be tuned smaller if it can be controlled over voltage / temp / pulse width.
The values are conservative to make sure all boards don't have cross-conduction - probably could reduce it still a few more ns.

The discrete version has a single PWM input - since deadtime is controlled and minimized, the negative switch node voltage is too short duration to be an issue - those Si schottky diodes are pretty slow . The board can be modified for two input operation, which will require an optional high side regulator (footprint for Mic5213) to avoid OV on HS with extended dead-time (such as isolated half-bridge application).

There are many options for improving the 'usability' of our devices.
Wider pitch, better miller ratio, higher VTH and VGSmax, larger / better thermal package etc. Some are easier to do than others and are being looked into...

We are working with one or more companies to develop modules with our die and either controller / driver in a single package. All I can say - sorry.

On a personal note, I did spend a few years working on class-D and found it a unique field - like EMI/C - it is still a bit more art than science. Never had a good ear for it, but worked for someone who had a favorite sub-50Hz frequency and would talk about the 'color' or the music.

[smms73]

I mean a driver with a fet in a integrated circuit package, DOH!

Very nice pcb, i like it very much elevator, congratulations, i think you are almost there.
Try to use thicker traces in the connection between the lt5113 and the fet.

wen i get free time i will send you a schematic of a dead time generator with only one variable resistor. maybe Monday. This weekend i will make some wine , not much time for electronic.

just discover this now:
http://epc-co.com/epc/documents/arti...erformance.pdf

[smms73]

thanks for answer so fast EPCguy. It is a little bit late in this part of the world. I will read your post with attention. And we will speak again soon (i hope). thanks