Minimizing distortion in self-oscillating switching amplifiers - some thoughts...

[ViennaTom]

I have found the following thesis that I think has some definitely good points.

http://www.student.dtu.dk/~ksme/diy/...amp_master.pdf

Since it is available on the net, I think it should be ok to place a link here, especially since I (a class D-crazy guy) found it very interesting and "enlightening". Am I right?
I still have some detailed q's here, that should go out to the real experts there, of whom I know there are several on this forum.

Page 9: In general, high loop gain means high ratio between amplitude at fs and a given point down in the audio band. But: The higher the loop gain, the less millivolts will remain at the comparator input. Am I right stating that the "holy grail" of distortionless Class-D also means finding comparators that are ever more sensitive at the input and can switch fast and reliably even if there is only less and less millivolts of overdrive? In other words, today's hi-performance devices may still not be good enough in the quest for ever higher loop gain? Or is this even the very reason why some designers do build their own comparators in descrete transistor-style (!)? (which is hard to
understand for me anyway, since I am always trying to understand those things as based on "functional blocks"...)

Page 11, fig. 3.3: Does this control topology fall under the UCD patent? I think so, but its not mentioned, at least not on this page.

Page 14, fig. 4.2 a: With the poles and zeroes added, the whole loop seems to have exactly no phase margin at ~40kHz (coincidentially? on purpose?). The whole thing to me seems to be not feasible in practice, since I guess the phase would go below -180° if the load went slighly above 8 Ohms yielding steeper phase decay at the LC stage? Any good reason why it wouldn't oscillate there?

...Can't wait long enough for your comments on these points!..

[nigelwright7557]

Keep deadtime to a minimum.

[Ouroboros]

<Quoted from ViennaTom>
Page 14, fig. 4.2 a: With the poles and zeroes added, the whole loop seems to have exactly no phase margin at ~40kHz (coincidentially? on purpose?). The whole thing to me seems to be not feasible in practice, since I guess the phase would go below -180° if the load went slighly above 8 Ohms yielding steeper phase decay at the LC stage? Any good reason why it wouldn't oscillate there?

This can be a problem with UCD-style amplifiers if asked to drive a large signal into a high impedance load. Typically seen when using this type of amplifer to drive 100V PA speaker lines through a step-up transformer. You have to ensure that even with no load connected at the secondary of the transformer, that the amplifier does not flip to a stable oscillation at slightly above the resonant frequency of the output filter. Careful tweaking of the lead/lag networks can do this, but you are limited in the amount of open-loop gain you can use and still keep the amplifer stable under all load and signal conditions.
Brunos latest (ncore) design concept seems to be one way to improve matters.

[ViennaTom]

So can we agree that these kinds of "improved" control designs with higher loop gain, but less phase margin are only useful if the speaker is well-known, will always stay connected and stay the same, e. g. for an active speaker system or the like. For a stand-alone amp unit that has to work with hundreds of different speakers / X-overs, cables, etc (is shorted, overloaded, ...regularly.....), I d stongly guess, that zero phase margin at a purely resistive 8 Ohm load does not suffice to cover all possible ways of (ab)use...
Or is there any kind of secret "magic" trick to tame these high-loop gain control designs?

[Ouroboros]

You can certainly make a 'UCD' style of amplifier stable into a wide range of normal loudspeaker impedances. If you have an application where the amplifier might be driven into voltage clipping into an open circuit load then you have to be more careful.

Increasing the loop gain to decrease the amplifer distortion will, not surprisingly, degrade the stability margin. Bruno Putzeys new 'ncore' design (US patent 2011/0068864) seems to have circuit features to improve this aspect of the performance.

[Ouroboros]

Don't forget that for a high impedance load, the output filter phase transition from 0 to -180 degrees is quite sharp, so anything that adds a bit more phase shift at this low frequency where the O/L gain is quite high can easily result in oscillation at 30-40kHz. This oscillation can (as I have found) soon overheat the output filter capacitors!

[ViennaTom]

Fig. 6.4.:

Is it really stable under all conditions having two 180°-crossings? On page 24 it says: "Two 180° crossings are present, but only the fastest one will start the amp oscilllating". Why? And if so, why is there any need to recover the phase using proportional feed-forward around the LC-filter, if the phase crossing 180° doesn't mind anyway?
Oh, I think I should start my simulator but to find out those things needs many days of simulating... too bad, my main profession does not let me work work on these issues full time...

[Ouroboros]

I have certainly seen full-bridge UCD-style amplifiers start oscillating at the lower frequency when subjected to high input signals and a very high impedance load!

[Pabo]

Vienna Tom

"Am I right stating that the "holy grail" of distortionless Class-D also means finding comparators that are ever more sensitive at the input and can switch fast and reliably even if there is only less and less millivolts of overdrive?"

This is one way to increase loop gain as loop gain in a global phase modulated topology can be seen as the ration between the supply lines and the modulation signal (goes for all analog topologies btw). This i why adding passive poles (like UcD) improves linearity with more than 6dB.

The disadvantages with this approach is (as you mention) increased demands on the comparator but also higher noise sensitivity. The later can be problematic if you want to place two channels close to eachother.

My approach is to never reduce the modulation signal amplitude more than necessary and instead increase loop gain in other ways. There is one more input on the comparator.

[ViennaTom]

again at Fig. 6.4.:

If a structure like this is worked out into a full schematic, built and sold. What patents would be infringed?