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Old 19th August 2010, 09:44 AM   #1
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Default tas5630 pcb for verification

Hi please anybody verify my PCB design for TI class d amplifier. I have already designed a PCB with single side. Its works but it sound is very low and soon the chip get damaged..

So i decide to design my PCB with double side and closer filter capacitors.

Here my old PCB So please give me a solution for the PCB design problem.......

Thank you

regards
udhay
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Old 19th August 2010, 01:04 PM   #2
marce is online now marce  United Kingdom
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My initial comment would be if you can remove the tracks causing splits in the bottom ground plane, it would be beneficial for EMC and signal integrity.
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Old 20th August 2010, 01:46 PM   #3
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Originally Posted by marce View Post
My initial comment would be if you can remove the tracks causing splits in the bottom ground plane, it would be beneficial for EMC and signal integrity.
Thanks for your reply

Are you talking about the bottom track. Can you mention the specific track in my PCB image. If it is the problem means i cont draw the track in another route so i can remove the track and i will connect a wire directly to the points.

Is there any other problems. May i use the same schematic from the slau290 TI EVM schematic....

Thanks and regards
Udhay
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Old 20th August 2010, 03:33 PM   #4
Eva is offline Eva  Spain
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The inductance of a stacked film capacitor is roughly proportional to its lead spacing at 1.2nH per mm or so.

Output capacitors with 10mm lead spacing are not a good idea. Try simulating the frequency response of an output filter including capacitor inductance and you will see the effect on RF attenuation. The filter will lose the 12dB/oct attenuation above f=1/(2*3.1415*sqr(C_cap*L_cap)). So L_cap has to be made 4 times smaller to rise f by one octave (*2).

I recommend paralleling several same-value smaller film capacitors with as short lead spacing as possible (typ. 5mm).

Film capacitors with long lead spacing are nearly useless for switched mode power supplies and class D amplifiers.
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Old 20th August 2010, 03:36 PM   #5
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i use 2.5mm lead spacing, you dont get lower inductance than that in through hole mount. Next step would be smd capacitors.
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Old 20th August 2010, 04:11 PM   #6
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Hi eva but the TI EVM uses same capacitor pitch. Why they design like this. Actually i dont have idea about the output LC filter. If it is a problem means i try to reduce the capacitor pitch as you mentioned. Thank you.

Do you have any idea about the inductor core. Is there any core material available in Mouser or digikey.

regards
udhay
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Old 22nd August 2010, 07:37 PM   #7
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May i use this modified PCB design with continuous ground track....
Please anybody verify this......

Thanks & regards
Udhay
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